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Renesas M16C/62P Group, Hardware Manual

The Renesas M16C/62P Group is a high-performance microcontroller series that offers advanced features for various applications. Users can access the detailed Hardware Manual for this product for free download from manualshive.com. This manual provides comprehensive information on the product specifications, functions, and usage, ensuring optimal performance.

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M16C/62P Group (M16C/62P, M16C/62PT)

9. Memory Space Expansion Function 

Rev.2.41

Jan 10, 2006

Page 80 of 390

REJ09B0185-0241

Figure 9.8

Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (2)

000000h

080000h

100000h

180000h

200000h

280000h

380000h

3FFFFFh

3C0000h

340000h

2C0000h

240000h

1C0000h

140000h

0C0000h

040000h

Data

OFS bit in DBR
register = 0

OFS bit in DBR
register = 1

300000h

Program

or data

A18

CS Output

Address Output

OFS

Access

Area

Output from the Microcomputer Pins

CS3

CS2

CS1

A19

A17

A16 A15 to A0

Bank

Number

0

0

1

1

0

1

2

0

1

3

0

1

4

0

1

5

0

1

6

0

1

7

0

Internal ROM access

40000h

0

0000h

000000h

0

0

0

1

0

0

Internal ROM access

040000h

0

0

0

1

0

0

0

40000h

0000h

080000h

0

0

1

0

1

0

0

40000h

0000h

0C0000h

0

0

1

1

0

0

0

40000h

0000h

100000h

0

1

0

0

1

0

0

40000h

0000h

140000h

0

1

0

1

0

0

0

40000h

0000h

180000h

0

1

1

0

1

0

0

40000h

0000h

1C0000h

0

1

1

1

0

0

0

40000h

0000h

200000h

1

0

0

0

1

0

0

40000h

0000h

240000h

1

0

0

1

0

0

0

40000h

0000h

280000h

1

0

1

0

1

0

0

40000h

0000h

2C0000h

1

0

1

1

0

0

0

40000h

0000h

300000h

1

1

0

0

1

0

0

40000h

0000h

340000h

1

1

0

1

0

0

0

40000h

0000h

40000h

380000h

1

1

1

0

1

0

0

0000h

80000h

Internal ROM access

3C0000h

1

1

1

1

0

0

0

0000h

7FFFFh

FFFFh

0

0

0

0

1

1

1

03FFFFh

0

0

0

1

0

1

1

7FFFFh

FFFFh

07FFFFh

0

0

1

0

1

1

1

7FFFFh

FFFFh

0BFFFFh

0

0

1

1

0

1

1

7FFFFh

FFFFh

0FFFFFh

0

1

0

0

1

1

1

7FFFFh

FFFFh

13FFFFh

0

1

0

1

0

1

1

7FFFFh

FFFFh

17FFFFh

0

1

1

0

1

1

1

7FFFFh

FFFFh

1BFFFFh

0

1

1

1

0

1

1

7FFFFh

FFFFh

1FFFFFh

1

0

0

0

1

1

1

7FFFFh

FFFFh

23FFFFh

1

0

0

1

0

1

1

7FFFFh

FFFFh

27FFFFh

1

0

1

0

1

1

1

7FFFFh

FFFFh

2BFFFFh

1

0

1

1

0

1

1

7FFFFh

FFFFh

2FFFFFh

1

1

0

0

1

1

1

7FFFFh

FFFFh

33FFFFh

1

1

0

1

0

1

1

7FFFFh

FFFFh

37FFFFh

1

1

1

0

1

1

1

7FFFFh

FFFFh

3BFFFFh

FFFFFh

Internal ROM access

1

1

1

1

0

1

1

FFFFh

3FFFFFh

A20

A19

A18

N.C.

A17

A16 A15 to A0

Address Input for 4-Mbyte ROM

Address input for

4-Mbyte ROM

A21

7FFFFh

bank 0
(256 Kbytes)

bank 1
(256 Kbytes)

bank 2
(256 Kbytes)

bank 3
(256 Kbytes)

bank 4
(256 Kbytes)

bank 5
(256 Kbytes)

bank 6
(256 Kbytes)

bank 7
(256 Kbytes)

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

bank 0
(256 Kbytes)

bank 1
(256 Kbytes)

bank 2
(256 Kbytes)

bank 3
(256 Kbytes)

bank 4
(256 Kbytes)

bank 5
(256 Kbytes)

bank 6
(256 Kbytes)

bank 7
(256 Kbytes)

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7

1

40000h

80000h

7FFFFh

FFFFFh

N.C.: No connected

ROM address

Microcomputer address

Memory expansion mode where PM13 =1

Program

only

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010-62245566 13810019655

Summary of Contents for M16C/62P Group

Page 1: ...ify that this is the most updated document available REJ09B0185 0241 16 M16C 62P Group M16C 62P M16C 62PT Hardware Manual RENESAS 16 BIT SINGLE CHIP MICROCOMPUTER M16C FAMILY M16C 60 SERIES Rev 2 41 R...

Page 2: ...echnical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attentio...

Page 3: ...ed to the bit concerned As the bit may be use for future functions set to 0 when writing to this bit Do not set to this value The operation is not guaranteed when a value is set Function varies depend...

Page 4: ...ifications pin assignments memory maps peripheral specifications electrical characteristics timing charts Software Manual Detailed description of assembly instructions and microcomputer performance of...

Page 5: ...Pointer ISP 31 2 7 Static Base Register SB 31 2 8 Flag Register FLG 31 2 8 1 Carry Flag C Flag 31 2 8 2 Debug Flag D Flag 31 2 8 3 Zero Flag Z Flag 31 2 8 4 Sign Flag S Flag 31 2 8 5 Register Bank Se...

Page 6: ...4 7 2 Setting Processor Modes 55 8 Bus 59 8 1 Bus Mode 59 8 1 1 Separate Bus 59 8 1 2 Multiplexed Bus 59 8 2 Bus Control 60 8 2 1 Address Bus 60 8 2 2 Data Bus 60 8 2 3 Chip Select Signal 60 8 2 4 Rea...

Page 7: ...n Detect Function 103 10 6 1 Operation When CM27 bit 0 Oscillation Stop Detection Reset 103 10 6 2 Operation When CM27 bit 0 Oscillation Stop and Re oscillation Detect Interrupt 103 10 6 3 How to Use...

Page 8: ...8 Key Input Interrupt 121 12 9 Address Match Interrupt 122 13 Watchdog Timer 124 13 1 Count source protective mode 125 14 DMAC 126 14 1 Transfer Cycles 132 14 1 1 Effect of Source and Destination Add...

Page 9: ...I O4 227 17 2 1 SI Oi Operation Timing 231 17 2 2 CLK Polarity Selection 231 17 2 3 Functions for Setting an SOUTi Initial Value 232 18 A D Converter 233 18 1 Mode Description 238 18 1 1 One Shot Mode...

Page 10: ...22 3 CPU Rewrite Mode 275 22 3 1 EW0 Mode 276 22 3 2 EW1 Mode 276 22 3 3 Flash memory Control Register FIDR FMR0 and FMR1 registers 276 22 3 4 Precautions on CPU Rewrite Mode 284 22 3 5 Software Comma...

Page 11: ...in DMiCON Register 369 24 9 Timers 370 24 9 1 Timer A 370 24 9 2 Timer B 372 24 10 Serial interface 373 24 10 1 Clock Synchronous Serial I O 373 24 10 2 UART 374 24 10 3 SI O3 SI O4 374 24 11 A D Con...

Page 12: ...to access 380 24 15 12Writing in the user ROM area 380 24 15 13DMA transfer 381 24 15 14Regarding Programming Erasing Endurance and Execution Time 381 24 16 Noise 382 25 Differences Depending on Manu...

Page 13: ...terrupt Control Register UART1 BUS Collision Detection Interrupt Control Register TB4IC U1BCNIC 111 0047h Timer B3 Interrupt Control Register UART0 BUS Collision Detection Interrupt Control Register T...

Page 14: ...TB3 157 0351h 0352h Timer B4 Register TB4 157 0353h 0354h Timer B5 Register TB5 157 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh Timer B3 Mode Register TB3MR 157 035Ch Timer B4 Mode Register TB4MR 157 0...

Page 15: ...er DM1SL 129 03BBh 03BCh CRC Data Register CRCD 253 03BDh 03BEh CRC Input Register CRCIN 253 03BFh Address Register Symbol Page 03C0h A D Register 0 AD0 237 03C1h 03C2h A D Register 1 AD1 237 03C3h 03...

Page 16: ...ble of executing instructions at high speed In addition this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability makes it suitable for control of va...

Page 17: ...ts x 6 channels Three phase motor control circuit Serial Interface 3 channels Clock synchronous UART I2C bus 1 IEBus 2 2 channels Clock synchronous A D Converter 10 bit A D converter 1 circuit 26 chan...

Page 18: ...us 1 IEBus 2 2 channels Clock synchronous A D Converter 10 bit A D converter 1 circuit 26 channels D A Converter 8 bits x 2 channels DMAC 2 channels CRC Calculation Circuit CCITT CRC Watchdog Timer 15...

Page 19: ...2 2 channels Clock synchronous 1 channel is only transmission A D Converter 10 bit A D converter 1 circuit 26 channels D A Converter 8 bits x 2 channels DMAC 2 channels CRC Calculation Circuit CCITT...

Page 20: ...al I O 8 bits X 3 channels System clock generation circuit XIN XOUT XCIN XCOUT PLL frequency synthesizer On chip oscillator M16C 60 series16 bit CPU core Port P0 8 Port P1 8 Port P2 8 8 8 8 Port P6 8...

Page 21: ...series16 bit CPU core Port P0 8 Port P2 8 Port P3 8 Port P4 4 Port P5 8 Port P6 8 CRC arithmetic circuit CCITT Polynomial X16 X12 X5 1 Memory 4 7 7 8 Port P10 Port P9 Port P8 Port P7 Port P8_5 ROM 1 R...

Page 22: ...0622M6P XXXFP 48 Kbytes 4 Kbytes PRQP0100JB A Mask ROM version M30622M6P XXXGP PLQP0100KB A M30622M8P XXXFP 64 Kbytes 4 Kbytes PRQP0100JB A M30622M8P XXXGP PLQP0100KB A M30623M8P XXXGP PRQP0080JA A M3...

Page 23: ...B A M30626MHP XXXGP PLQP0100KB A M30627MHP XXXGP PLQP0128KB A M30626MJP XXXFP D 512 Kbytes 31 Kbytes PRQP0100JB A M30626MJP XXXGP D PLQP0100KB A M30627MJP XXXGP D PLQP0128KB A M30622F8PFP 64K 4 Kbytes...

Page 24: ...85 C version M3062CM6T XXXGP D PLQP0100KB A M3062EM6T XXXGP P PRQP0080JA A M3062CM8T XXXFP D 64 Kbytes 4 Kbytes PRQP0100JB A M3062CM8T XXXGP D PLQP0100KB A M3062EM8T XXXGP P PRQP0080JA A M3062CMAT XXX...

Page 25: ...JB A Mask ROM version V Version High reliability 125 C version M3062CM6V XXXGP P PLQP0100KB A M3062EM6V XXXGP P PRQP0080JA A M3062CM8V XXXFP P 64 Kbytes 4 Kbytes PRQP0100JB A M3062CM8V XXXGP P PLQP010...

Page 26: ...on and ROMless version Memory type M Mask ROM version F Flash memory version S ROM less version Type No M 3 0 6 2 6 M H P X X X F P M16C 62 P Group M16C Family Shows RAM capacity pin count etc Numeric...

Page 27: ...85 C D7 1 000 10 000 40 C to 85 C 40 C to 85 C D9 20 C to 85 C 20 C to 85 C U3 Lead free 100 100 0 C to 60 C 40 C to 85 C U5 20 C to 85 C U7 1 000 10 000 40 C to 85 C 40 C to 85 C U9 20 C to 85 C 20 C...

Page 28: ...y Version T Version B Lead included 100 0 C to 60 C 100 0 C to 60 C 40 C to 85 C V Version 40 C to 125 C T Version B7 1 000 10 000 40 C to 85 C 40 C to 85 C V Version 40 C to 125 C 40 C to 125 C T Ver...

Page 29: ...1 P10_2 AN2 P10_3 AN3 P9_3 DA0 TB3IN P9_4 DA1 TB4IN P9_5 ANEX0 CLK4 P9_6 ANEX1 SOUT4 P9_1 TB1IN SIN3 P9_2 TB2IN SOUT3 P8_0 TA4OUT U P6_0 CTS0 RTS0 P6_4 CTS1 RTS1 CTS0 CLKS1 P8_2 INT0 P8_3 INT1 P8_5 NM...

Page 30: ...P14_0 13 BYTE 14 CNVSS 15 XCIN P8_7 16 XCOUT P8_6 17 RESET 18 XOUT 19 VSS 20 XIN 21 VCC1 22 P8_5 NMI 23 P8_4 INT2 ZP 24 P8_3 INT1 25 P8_2 INT0 26 P8_1 TA4IN U 27 P8_0 TA4OUT U 28 P7_7 TA3IN 29 P7_6 TA...

Page 31: ...P12_6 64 P12_5 65 P4_7 CS3 66 P4_6 CS2 67 P4_5 CS1 68 P4_4 CS0 69 P4_3 A19 70 P4_2 A18 71 P4_1 A17 72 P4_0 A16 73 P3_7 A15 74 P3_6 A14 75 P3_5 A13 76 P3_4 A12 77 P3_3 A11 78 P3_2 A10 79 P3_1 A9 80 P1...

Page 32: ..._2 D10 102 P1_1 D9 103 P1_0 D8 104 P0_7 AN0_7 D7 105 P0_6 AN0_6 D6 106 P0_5 AN0_5 D5 107 P0_4 AN0_4 D4 108 P0_3 AN0_3 D3 109 P0_2 AN0_2 D2 110 P0_1 AN0_1 D1 111 P0_0 AN0_0 D0 112 P11_7 113 P11_6 114 P...

Page 33: ...2 P3_5 A13 P3_6 A14 P3_7 A15 P4_0 A16 P4_1 A17 P4_2 A18 P4_3 A19 P7_4 TA2OUT W P7_6 TA3OUT P5_6 ALE P7_7 TA3IN P5_5 HOLD P5_4 HLDA P5_3 BCLK P5_2 RD VCC2 VSS P5_7 RDY CLKOUT P4_5 CS1 P4_6 CS2 P4_7 CS3...

Page 34: ...2 P3_5 A13 P3_6 A14 P3_7 A15 P4_0 A16 P4_1 A17 P4_2 A18 P4_3 A19 P7_4 TA2OUT W P7_6 TA3OUT P5_6 ALE P7_7 TA3IN P5_5 HOLD P5_4 HLDA P5_3 BCLK P5_2 RD VCC2 VSS P5_7 RDY CLKOUT P4_5 CS1 P4_6 CS2 P4_7 CS3...

Page 35: ...NMI 18 16 P8_4 INT2 ZP 19 17 P8_3 INT1 20 18 P8_2 INT0 21 19 P8_1 TA4IN U 22 20 P8_0 TA4OUT U 23 21 P7_7 TA3IN 24 22 P7_6 TA3OUT 25 23 P7_5 TA2IN W 26 24 P7_4 TA2OUT W 27 25 P7_3 TA1IN V CTS2 RTS2 28...

Page 36: ...67 65 P2_5 AN2_5 A5 D5 D4 68 66 P2_4 AN2_4 A4 D4 D3 69 67 P2_3 AN2_3 A3 D3 D2 70 68 P2_2 AN2_2 A2 D2 D1 71 69 P2_1 AN2_1 A1 D1 D0 72 70 P2_0 AN2_0 A0 D0 73 71 P1_7 INT5 D15 74 72 P1_6 INT4 D14 75 73 P...

Page 37: ...0JA A 80P6S A NOTES 1 P7_0 and P7_1 are N channel open drain output pins PIN CONFIGURATION top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 75 76 77 78 79 80 VCC1 XIN XOUT VSS RESET CNVSS BYTE P8_7...

Page 38: ...9 RESET 10 XOUT 11 VSS 12 XIN 13 VCC1 14 P8_5 NMI 15 P8_4 INT2 ZP 16 P8_3 INT1 17 P8_2 INT0 18 P8_1 TA4IN 19 P8_0 TA4OUT 20 P7_7 TA3IN 21 P7_6 TA3OUT 22 P7_1 TA0IN TB5IN RXD2 SCL2 23 P7_0 TA0OUT TXD2...

Page 39: ...AN2_7 53 P2_6 AN2_6 54 P2_5 AN2_5 55 P2_4 AN2_4 56 P2_3 AN2_3 57 P2_2 AN2_2 58 P2_1 AN2_1 59 P2_0 AN2_0 60 P0_7 AN0_7 61 P0_6 AN0_6 62 P0_5 AN0_5 63 P0_4 AN0_4 64 P0_3 AN0_3 65 P0_2 AN0_2 66 P0_1 AN0...

Page 40: ...pin to VSS when an single chip mode Bus control pins 4 D0 to D7 I O VCC2 Inputs and outputs data D0 to D7 when these pins are set as the separate bus D8 to D15 I O VCC2 Inputs and outputs data D8 to...

Page 41: ...the NMI interrupt Pin states can be read by the P8_5 bit in the P8 register Key input interrupt input KI0 to KI3 I VCC1 Input pins for the key input interrupt Timer A TA0OUT to TA4OUT I O VCC1 These a...

Page 42: ...in external op amp connection mode ANEX1 I VCC1 This is the extended analog input pin for the A D converter D A converter DA0 DA1 O VCC1 This is the output pin for the D A converter I O port P0_0 to P...

Page 43: ...XCIN and XCOUT 3 To use the external clock input the clock from XCIN and leave XCOUT open Sub clock output XCOUT O VCC1 Clock output CLKOUT O VCC2 The clock of the same cycle as fC f8 or f32 is outpu...

Page 44: ...pin for the A D converter and is the output in external op amp connection mode ANEX1 I VCC1 This is the extended analog input pin for the A D converter D A converter DA0 DA1 O VCC1 This is the output...

Page 45: ...sters R1H and R1L are the same as R0H and R0L Conversely R2 and R0 can be combined for use as a 32 bit data register R2R0 R3R1 is the same as R2R0 Data Registers 1 Address Registers 1 Frame Base Regis...

Page 46: ...ted by the U flag of FLG 2 7 Static Base Register SB SB is configured with 16 bits and is used for SB relative addressing 2 8 Flag Register FLG FLG consists of 11 bits indicating the CPU status 2 8 1...

Page 47: ...request is accepted or an INT instruction for software interrupt Nos 0 to 31 is executed 2 8 9 Processor Interrupt Priority Level IPL IPL is configured with three bits for specification of up to eigh...

Page 48: ...h to FFFDBh This vector is used by the JMPS or JSRS instruction For details refer to the M16C 60 and M16C 20 Series Software Manual In memory expansion and microprocessor modes some areas are reserved...

Page 49: ...elect Control Register 6 CSR 00000001b 0009h Address Match Interrupt Enable Register AIER XXXXXX00b 000Ah Protect Register PRCR XX000000b 000Bh Data Bank Register 6 DBR 00h 000Ch Oscillation Stop Dete...

Page 50: ...D Conversion Interrupt Control Register ADIC XXXXX000b 004Fh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b 0050h UART2 Receive Interrupt Control Register S2RIC XXXXX000b 0051h UART0 Trans...

Page 51: ...2 FIDR XXXXXX00b 01B5h Flash Memory Control Register 1 2 FMR1 0X00XX0Xb 01B6h 01B7h Flash Memory Control Register 0 2 FMR0 00000001b 01B8h Address Match Interrupt Register 2 RMAD2 00h 01B9h 00h 01BAh...

Page 52: ...Xb 035Fh Interrupt Factor Select Register IFSR 00h 0360h SI O3 Transmit Receive Register S3TRR XXh 0361h 0362h SI O3 Control Register S3C 01000000b 0363h SI O3 Bit Rate Generator S3BRG XXh 0364h SI O4...

Page 53: ...er TA3MR 00h 039Ah Timer A4 Mode Register TA4MR 00h 039Bh Timer B0 Mode Register TB0MR 00XX0000b 039Ch Timer B1 Mode Register TB1MR 00XX0000b 039Dh Timer B2 Mode Register TB2MR 00XX0000b 039Eh Timer B...

Page 54: ...gister 1 ADCON1 00h 03D8h D A Register 0 DA0 00h 03D9h 03DAh D A Register 1 DA1 00h 03DBh 03DCh D A Control Register DACON 00h 03DDh 03DEh Port P14 Control Register 3 PC14 XX00XXXXb 03DFh Pull Up Cont...

Page 55: ...e RESET pin while writing data to the internal RAM the internal RAM is in an indeterminate state Figure 5 1 shows an Example Reset Circuit Figure 5 2 shows a Reset Sequence Table 5 1 lists Pin Status...

Page 56: ...ycles are needed BCLK Address Address Address Microprocessor mode BYTE H Microprocessor mode BYTE L Single chip mode XIN RESET RD WR CS0 RD WR CS0 Content of reset vector BCLK 28cycles FFFFCh FFFFDh F...

Page 57: ...S R ms The same pins and registers are reset by the hardware reset 1 and brown out detection reset hardware reset 2 and are also placed in the same reset state The microcomputer cannot exit stop mode...

Page 58: ...in the CM0 register is set to 1 reset and the watchdog timer underflows Then the microcomputer executes the program in an address determined by the reset vector In the watchdog timer reset the microc...

Page 59: ...a Register R0 Address Register A0 Frame Base Register FB Program Counter PC Interrupt Table Register INTB User Stack Pointer USP Interrupt Stack Pointer ISP Static Base Register SB Flag Register FLG 0...

Page 60: ...e detection circuit detects VCC1 is above or below Vdet4 This signal generates the low voltage detection interrupt The VC13 bit in the VCR1 register determines whether VCC1 is above or below Vdet4 The...

Page 61: ...age detection hardw are reset 2 set the VC26 bit to 1 reset level detection circuit enable Write to this register after setting the PRC3 bit in the PRCR register to 1 w rite enable 0 Bit Name VCR2 Sym...

Page 62: ...16 1 0 CPU clock divided by 32 1 1 CPU clock divided by 64 RW DF1 RW b7 b6 Nothing is assigned When w rite set to 0 When read their contents are 0 Write to this register after setting the PRC3 bit in...

Page 63: ...eset Signal VC13 bit in VCR1 register VC26 bit in VCR2 register 1 VC27 bit in VCR2 register Set to 1 by program reset level detect circuit enable Set to 1 by program Low voltage detection circuit enab...

Page 64: ...pin is detected to be above Vdet4 The microcomputer then exits stop mode Table 6 1 shows Low Voltage Detection Interrupt Request Generation Conditions The DF1 to DF0 bits in the D4INT register determi...

Page 65: ...tchdog timer underflow signal D43 D41 CM02 WAIT instruction wait mode D40 VCC1 VREF Noise Rejection Rejection Range 200 ns Low Voltage detection signal The Low Voltage detection signal becomes H when...

Page 66: ...when the voltage applied rises to Vdet4 or above set the CM10 bit to 1 when VC13 bit is 0 VCC1 Vdet4 6 3 Limitations on Exiting Wait Mode The low voltage detection interrupt is immediately generated a...

Page 67: ...e 6 7 shows Cold Start up Warm Start up Determine Function Block Diagram Figure 6 8 shows the Cold Start up Warm Start up Determine Function Operation Example Figure 6 9 shows WDC Register Figure 6 7...

Page 68: ...art Discrimination Flag 1 2 0 Cold Start 1 Warm Start b7 b6 b5 b4 b3 b2 b1 b0 0 The WDC5 bit is set to 0 cold start w hen pow er is turned on and can be set to 1 by program only WDC7 b6 Reserved Bit S...

Page 69: ...Features of Processor Modes Processor Modes Access Space Pins which are Assigned I O Ports Single Chip Mode SFR Internal RAM Internal ROM All pins are I O ports or peripheral function I O pins Memory...

Page 70: ...1 to PM00 bits cannot be rewritten to 01b memory expansion mode or 11b microprocessor mode at the same time the PM07 to PM02 bits are rewritten Note also that these bits cannot be rewritten to enter m...

Page 71: ...Select Bit 2 Write to this register after setting the PRC1 bit in the PRCR register to 1 w rite enable RW Setting this bit to 1 resets the microcomputer When read its content is 0 Softw are Reset Bit...

Page 72: ...he access area is changed by the PM13 bit as listed in the table below RW PM11 RW PM13 RW Memory Area Expansion Bit 3 Port P3_7 to P3_4 Function Select Bit 3 Internal Reserved Area Expansion Bit 6 0 A...

Page 73: ...XXXXXh 12 Kbytes 033FFh 20 Kbytes 03FFFh 2 10 Kbytes 02BFFh 24 Kbytes 03FFFh 2 384 Kbytes D0000h 2 512 Kbytes D0000h 2 Internal RAM Internal ROM 4 Kbytes 013FFh 5 Kbytes 017FFh 31 Kbytes 03FFFh 2 48 K...

Page 74: ...level on BYTE pin is low 16 bit data bus D0 to D7 and A1 to A8 are multiplexed D8 to D15 are not multiplexed Do not use D8 to D15 External devices connecting to a multiplexed bus are allocated to onl...

Page 75: ...put on the BYTE pin is low data bus is 16 bits wide 16 lines D0 to D15 comprise the data bus Do not change the input level on the BYTE pin while in operation 8 2 3 Chip Select Signal The chip select h...

Page 76: ...the CSiW bit to 0 w ith w ait state When the CSiW bit 0 w ith w ait state the number of w ait states can be selected using the CSEi1W to CSEi0W bits in the CSEregister RW CS3W 0 With w ait state 1 Wi...

Page 77: ...e external area indicated by CSj in the next cycle after accessing the external area indicated by CSi The address bus and the chip select signal both change state between these two cycles Example 2 To...

Page 78: ...nput L L H H Read data H L H Write 1 byte of data to an even address H H L Write 1 byte of data to an odd address H L L Write data to both even and odd addresses Table 8 4 Operation of RD WRL and BHE...

Page 79: ...dge of BCLK the remaining bus cycle is executed Figure 8 4 shows Example in which the Wait State was Inserted into Read Cycle by RDY Signal To use the RDY signal set the corresponding bit CS3W to CS0W...

Page 80: ...o separate accesses Figure 8 5 Bus Using Priorities NOTES 1 P11 to P14 are included in the 128 pin version 2 When I O port function is selected 3 The watchdog timer dose not stop when the PM22 bit in...

Page 81: ...Processor Mode Processor Mode Memory Expansion Mode or Microprocessor Mode Memory Expansion Mode PM05 to PM04 bits 00b separate bus bits 01b CS2 is for multiplexed bus and others are for separate bus...

Page 82: ...al Area Accessed Item SFR Accessed Internal ROM RAM Accessed A0 to A19 Address output Maintain status before accessed address of external area or SFR D0 to D15 When Read High impedance High impedance...

Page 83: ...Using Software Wait Figure 8 6 CSE Register Chip Select Expansion Control Register Address After Reset 001Bh 00h Bit Symbol Function RW NOTES 1 b3 b2 0 0 1 w ait 0 1 2 w aits 1 0 3 w aits 1 1 Do not...

Page 84: ...external areas are accessed with one wait state 5 When PM17 bit is set to 1 and accesses an external area set the CSiW i 0 to 3 bits to 0 with wait state Table 8 8 Bit and Bus Cycle Related to Softwa...

Page 85: ...arate Bus No Wait Setting 2 Separate Bus 1 Wait Setting Output Input NOTES 1 These example timing charts indicate bus cycle length After this bus cycle sometimes come read and write cycles in successi...

Page 86: ...E 3 Multiplexed Bus 3 Wait Setting Output NOTES 1 These example timing charts indicate bus cycle length After this bus cycle sometimes come read and write cycles in succession Bus cycle 1 Bus cycle 1...

Page 87: ...number which is to be accessed to read or write data Setting the OFS bit to 1 with offset allows the accessed address to be offset by 40000h In 4 Mbyte mode the CSi i 0 to 3 pin functions differently...

Page 88: ...t to 0 When read their contents are 0 Function OFS Offset Bit RW 0 Not offset 1 Offset BSR0 RW b5 b4 b3 0 0 1 Bank 1 0 1 1 Bank 3 1 0 1 Bank 5 1 1 1 Bank 7 b5 b4 b3 0 0 0 Bank 0 0 1 0 Bank 2 1 0 0 Ban...

Page 89: ...d external area 2 External area 10000h SFR Internal RAM Reserved area Reserved area Reserved external area 2 External area CS2 PM10 1 92 Kbytes CS0 Memory expansion mode 640 Kbytes Internal RAM Intern...

Page 90: ...BFFh 24 Kbytes 063FFh 384 Kbytes A0000h 512 Kbytes 80000h PM13 1 External area 10000h SFR Internal RAM Reserved area Reserved area External area CS2 PM10 1 92 Kbytes CS0 Memory expansion mode 320 Kbyt...

Page 91: ...0 08000h to 26FFFh When PM10 1 10000h to 26FFFh CS3 04000h to 07FFFh C0000h Other than the CS area 512 Kbytes X 8 banks 40000h to BFFFFh Other than the CS area 1 NOTES 1 The CS0 pin outputs a low sign...

Page 92: ...to 26FFFh CS3 No area 80000h Other than the CS area Memory expansion mode 256 Kbytes X 8 banks Two 256 Kbytes X 8 banks can be used by changing the offset Other than the CS area 1 Memory expansion mo...

Page 93: ...register to 1 offset allows the accessed address to be offset by 40000h so that even the data overlapping a bank boundary can be accessed in succession In memory expansion mode where the PM13 bit is...

Page 94: ...ddress Input for 4 Mbyte ROM Address input for 4 Mbyte ROM A21 Internal ROM access D0000h Internal ROM access DFFFFh 040000h 0 0 0 1 0 0 0 40000h 0000h 080000h 0 0 1 0 1 0 0 40000h 0000h 0C0000h 0 0 1...

Page 95: ...1 1 1 0 0 0 0000h 7FFFFh FFFFh 0 0 0 0 1 1 1 03FFFFh 0 0 0 1 0 1 1 7FFFFh FFFFh 07FFFFh 0 0 1 0 1 1 1 7FFFFh FFFFh 0BFFFFh 0 0 1 1 0 1 1 7FFFFh FFFFh 0FFFFFh 0 1 0 0 1 1 1 7FFFFh FFFFh 13FFFFh 0 1 0...

Page 96: ...1 0 40000h 0 1 0 1 0 0 40000h 0 1 1 0 1 0 40000h 0 1 1 1 0 0 40000h 1 0 0 0 1 0 40000h 1 0 0 1 0 0 40000h 1 0 1 0 1 0 40000h 1 0 1 1 0 0 40000h 1 1 0 0 1 0 40000h 1 1 0 1 0 0 40000h 40000h 1 1 1 0 1...

Page 97: ...lation Circuit Sub Clock Oscillation Circuit On chip oscillator PLL frequency synthesizer Use of Clock CPU clock source Peripheral function clock source CPU clock source Timer A B s clock source CPU c...

Page 98: ...8 1 16 1 32 PCLK0 1 PLL frequency synthesizer 0 1 CM21 1 CM11 CM21 0 On chip oscillator PLL clock Sub clock On chip oscillator clock BCLK PCLK0 0 f2 f1SIO PCLK1 1 PCLK1 0 f2SIO Main clock CLKOUT PM01...

Page 99: ...for detection as to w hether the main clock stops or not To stop the main clock set bits as follow s a Set the CM07 bit to 1 sub clock selected or the CM21 bit in the CM2 register to 1 On chip oscill...

Page 100: ...ck 5 RW b4 b2 Reserved Bit Set to 0 b3 b2 b1 b0 b7 b6 b5 b4 0 0 0 CM10 All Clock Stop Control Bit 4 6 0 Clock on 1 All clocks off stop mode RW RW CM15 XIN XOUT Drive Capacity Select Bit 2 0 LOW 1 HIGH...

Page 101: ...main clock the CM21 bit is set to 1 on chip oscillator clock if the main clock stop is detected If the CM20 bit is set to 1 and the CM23 bit is set to 1 main clock stops do not set the CM21 bit to 0 S...

Page 102: ...w aits w hen PLL clock 16MHz Once this bit is set to 1 it cannot be cleared to 0 in a program If the PM21 bit is set to 1 w riting to the follow ing bits has no effect CM02 bit in CM0 register CM05 b...

Page 103: ...7 bit 0 PLL turned off The value once w ritten to this bit cannot be modified Before setting this bit to 1 set the CM07 bit in the CM0 register to 0 main clock set the CM17 to CM16 bits in the CM1 reg...

Page 104: ...ff after switching the clock source for the CPU clock to a sub clock or on chip oscillator clock In this case XOUT goes H Furthermore because the internal feedback resistor remains on XIN is pulled H...

Page 105: ...k Connection Circuit After reset the sub clock is turned off At this time the feedback resistor is disconnected from the oscillator circuit To use the sub clock for the CPU clock set the CM07 bit in t...

Page 106: ...is used as the clock source for the CPU and peripheral function clocks After reset the PLL clock is turned off The PLL frequency synthesizer is activated by setting the PLC07 bit to 1 PLL operation W...

Page 107: ...e CM17 to CM16 bits to 00b main clock undivided and the CM06 bit to 0 CM16 and CM17 bits enabled 1 Set the PLC02 to PLC00 bits multiplying factor When PLL clock 16MHz Set the PM20 bit to 0 2 wait stat...

Page 108: ...ote that when entering stop mode from high or middle speed mode on chip oscillator mode or on chip oscillator low power dissipation mode or when the CM05 bit in the CM0 register is set to 1 main clock...

Page 109: ...k divided by 1 provides the CPU clock If the sub clock is on fC32 can be used as the count source for Timers A and B 10 4 1 2 PLL Operating Mode The main clock multiplied by 2 4 6 or 8 provides the PL...

Page 110: ...and CM06 bit is set to 1 divided by 8 mode simultaneously 2 The divide by n value can be selected the same way as in on chip oscillator mode Table 10 3 Setting Clock Related Bit and Modes Modes CM2 R...

Page 111: ...tering Wait Mode The microcomputer is placed into wait mode by executing the WAIT instruction When the CM11 bit 1 CPU clock source is the PLL clock be sure to clear the CM11 bit in the CM1 register to...

Page 112: ...xecuting the WAIT instruction 1 Set the ILVL2 to ILVL0 bits in the interrupt control register for peripheral function interrupts used to exit wait mode The ILVL2 to ILVL0 bits in all other interrupt c...

Page 113: ...in the CM2 register to 0 oscillation stop re oscillation detection function disable Also if the CM11 bit in the CM1 register is 1 PLL clock for the CPU clock source set the CM11 bit to 0 main clock fo...

Page 114: ...re entering stop mode On chip oscillator clock divided by 8 Figure 10 10 shows the State Transition from Normal Operating Mode to Stop Mode and Wait Mode Figure 10 11 shows the State Transition in Nor...

Page 115: ...7 1 CM16 1 Middle speed mode divide by 16 CPU clock f XIN 2 CM07 0 CM06 0 CM17 0 CM16 1 Middle speed mode divide by 2 CPU clock f XIN 8 Middle speed mode divide by 8 CM07 0 CM06 1 CM07 1 3 CM07 0 2 4...

Page 116: ...chip Oscillator Low Power Dissipation Mode Stop Mode Wait Mode Current State High Speed Mode Middle Speed Mode NOTE 8 9 NOTE 7 13 NOTE 3 15 16 NOTE 1 17 Low Speed Mode 2 8 11 NOTE 1 6 16 NOTE 1 17 Lo...

Page 117: ...nge disabled the following bits cannot be written to The CM02 bit CM05 bit and CM07 bit in the CM0 register The CM10 bit and CM11 bit in the CM1 register The CM20 bit in the CM2 register All bits in t...

Page 118: ...nction enabled the system is placed in the following state if the main clock comes to a halt Oscillation stop and re oscillation detect interrupt request occurs The on chip oscillator starts oscillati...

Page 119: ...ed At the same time the on chip oscillator starts oscillating In this case although the CPU clock is derived from the sub clock as it was before the interrupt occurred the peripheral function clocks n...

Page 120: ...the next instruction The PRC0 PRC1 and PRC3 bits are not automatically cleared to 0 by writing to any address They can only be cleared in a program Figure 11 1 PRCR Register Protect Register Symbol A...

Page 121: ...n UND instruction Overflow INTO instruction BRK instruction INT instruction Special Non maskable interrupt Peripheral function 1 Maskable interrupt NOTES 1 The peripheral functions in the microcompute...

Page 122: ...rupt A BRK interrupt occurs when executing the BRK instruction 12 2 4 INT Instruction Interrupt An INT instruction interrupt occurs when executing the INT instruction Software interrupt Nos 0 to 63 ca...

Page 123: ...n detection function refer to the 10 Clock Generation Circuit 12 3 1 5 12 3 1 5 Low Voltage Detection Interrupt Generated by the voltage detection circuit For details about the voltage detection circu...

Page 124: ...s interrupt because it is provided exclusively for use by development tools 2 If the contents of address FFFE7h is FFh program execution starts from the address shown by the vector in the relocatable...

Page 125: ...rs Timer B4 UART1 Bus Collision Detect 4 6 24 to 27 0018h to 001Bh 6 15 Timers 17 Serial Interface Timer B3 UART0 Bus Collision Detect 4 6 28 to 31 001Ch to 001Fh 7 SI O4 INT5 2 32 to 35 0020h to 0023...

Page 126: ...00b BCNIC 004Ah XXXXX000b DM0IC DM1IC 004Bh 004Ch XXXXX000b KUPIC 004Dh XXXXX000b ADIC 004Eh XXXXX000b S0TIC to S2TIC 0051h 0053h 004Fh XXXXX000b S0RIC to S2RIC 0052h 0054h 0050h XXXXX000b TA0IC to TA...

Page 127: ...b2 b1 b0 0 ILVL0 RW b2 b1 b0 0 0 0 Level 0 interrupt disabled 0 0 1 Level 1 0 1 0 Level 2 0 1 1 Level 3 1 0 0 Level 4 1 0 1 Level 5 1 1 0 Level 6 1 1 1 Level 7 ILVL1 RW ILVL2 RW Interrupt Priority Lev...

Page 128: ...e Interrupt Priority Levels Enabled by IPL The following are conditions under which an interrupt is accepted I flag 1 IR bit 1 interrupt priority level IPL The I flag IR bit ILVL2 to ILVL0 bits and IP...

Page 129: ...and U flags in the FLG register become as follows The I flag is set to 0 interrupt disabled The D flag is set to 0 single step interrupt disabled The U flag is set to 0 ISP selected However the U fla...

Page 130: ...t is Accepted Table 12 5 IPL Level That is Set to IPL When a Software or Special Interrupt is Accepted Interrupt Sources Level that is Set to IPL Watchdog Timer NMI Oscillation Stop and Re Oscillation...

Page 131: ...interrupt routine Use the PUSHM instruction and all registers except SP can be saved with a single instruction Figure 12 7 Stack Status Before and After Acceptance of Interrupt Request Address Conten...

Page 132: ...2 SP contains odd number SP Odd SP 1 Even SP 2 Odd SP 3 Even SP 4 Odd SP 5 Even Address Sequence in which order registers are saved 2 1 Finished saving registers in four operations 3 4 1 SP contains e...

Page 133: ...led at the same sampling points a timing to detect whether an interrupt request is generated or not the interrupt with the highest priority is acknowledged For maskable interrupts peripheral functions...

Page 134: ...lision SI O4 INT5 UART1 transmission NACK1 UART0 transmission NACK0 UART2 transmission NACK2 Key input interrupt DMA0 IPL I flag Watchdog timer DBC NMI Interrupt request accepted Lowest Priority of pe...

Page 135: ...Interrupt Polarity Sw itching Bit IFSR6 When setting this bit to 1 both edges make sure the POL bit in the INT0IC to INT5IC register are set to 0 falling edge IFSR7 RW RW IFSR0 Interrupt Request Facto...

Page 136: ...y on wake up function the function which gets the microcomputer out of wait or stop mode However if you intend to use the key input interrupt do not use P10_4 to P10_7 as analog input ports Figure 12...

Page 137: ...e 12 6 shows the Value of the PC that is Saved to the Stack Area when an Address Match Interrupt Request is Accepted Figure 12 13 shows the AIER AIER2 and RMAD0 to RMAD3 Registers Value of the PC that...

Page 138: ...s After Reset AIER2 01BBh XXXXXX00b Bit Symbol Bit Name Function RW Nothing is assigned When w rite set to 0 When read their contents are indeterminate Address Match Interrupt 2 Enable Bit 0 Interrupt...

Page 139: ...imer is however subject to an error due to the prescaler With main clock chosen for CPU clock on chip oscillator clock PLL clock With sub clock chosen for CPU clock For example when CPU clock 16 MHz a...

Page 140: ...write Writing a 1 has no effect nor is stop mode entered The watchdog timer does not stop when in wait mode or hold state Watchdog timer period Watchdog timer count 32768 On chip oscillator clock Watc...

Page 141: ...t control register so that even when interrupt requests are disabled and no interrupt request can be accepted DMA requests are always accepted Furthermore because the DMAC does not affect interrupts t...

Page 142: ...MA0 DMA1 DMA0 takes precedence Transfer Unit 8 bits or 16 bits Transfer Address Direction forward or fixed The source and destination addresses cannot both be in the forward direction Transfer Mode Si...

Page 143: ...w hen the DMS bit is 0 basic factor and the DSEL3 to DSEL0 bits are 0001b softw are trigger The value of this bit w hen read is 0 RW DMS DMA Request Factor Expansion Select Bit 0 Basic factor of requ...

Page 144: ...are Trigger The factors of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below DSEL3 to DSEL0 DMS 0 Basic Factor of Request DMS 1 Extended F...

Page 145: ...st one of the DAD and DSD bits must be 0 address direction fixed b7 b6 Nothing is assigned When w rite set to 0 When read their contents are 0 b7 b6 b5 b4 b3 b2 b1 b0 RW RW DMAS RW 1 Source Address Di...

Page 146: ...3 b7 b19 b3 b16 b0 b15 b7 b8 b0 b7 Function Set the destination address of transfer 00000h to FFFFFh RW Nothing is assigned When w rite set 0 When read their contents are 0 If the DAD bit in the DMiCO...

Page 147: ...tion is accomplished by transferring 8 bits of data twice Therefore this operation requires two bus cycles to read data and two bus cycles to write data Furthermore if the DMAC is to access the intern...

Page 148: ...se CPU use Source Destination Dummy cycle Source 1 2 When the transfer unit is 16 bits and the source address of transfer is an odd address or when the transfer unit is 16 bits and an 8 bit bus is use...

Page 149: ...PM20 bit in the PM2 register Table 14 2 DMA Transfer Cycles Transfer Unit Bus Width Access Address Single Chip Mode Memory Expansion Mode Microprocessor Mode No of Read Cycles No of Write Cycles No of...

Page 150: ...ither channel Table 14 4 lists the Timing at Which the DMAS Bit Changes State Whenever a DMA request is generated the DMAS bit is set to 1 DMA requested regardless of whether or not the DMAE bit is se...

Page 151: ...ansfer when a DMA0 request and DMA1 request are generated simultaneously After one DMA0 transfer is completed a bus arbitration is returned to the CPU When the CPU has completed one bus access a DMA1...

Page 152: ...Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter 00 01 10 11 TCK1 to TCK0 00 Timer mode 10 One shot tiemr mode 11 PWM mode 00...

Page 153: ...Pulse period pulse width measurement mode TCK1 1 0 TMOD1 to TMOD0 01 Event counter mode 00 Timer mode 10 Pulse period pulse width measurement mode TCK1 1 0 01 Event counter mode 00 Timer mode 10 Pulse...

Page 154: ...ounter mode 8 low order bits Counter Low Order Bits of Data Bus TAiUD Decrement TAk Overflow 1 Polarity Selector 00 01 11 10 TCK1 to TCK0 TB2 Overflow 1 00 01 10 11 TAiTGH to TAiTGL 11 01 01 00 0 1 MR...

Page 155: ...TAiOUT pin remains low and timer Ai interrupt requests are not generated either The same applies w hen the 8 high order bits of the timer TAi register are set to 00h w hile operating as an 8 bit pulse...

Page 156: ...he port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set to 0 input mode When not using the tw o phase pulse signal processing function set the bit corresponding to Timer A2 to...

Page 157: ...ed 1 Z phase input enabled Make sure the PD7_1 bit in the PD7 register is set to 0 input mode Overflow or underflow b7 b6 b5 b4 b3 b2 b1 Trigger Select Register Symbol Address After Reset TRGSR 0383h...

Page 158: ...After Reset CPSRF 0381h 0XXXXXXXb Bit Symbol Bit Name Function RW b7 b6 b5 b4 b3 b2 b1 b0 b6 b0 Nothing is assigned When w rite set to 0 When read their contents are indeterminate CPSR Clock Prescale...

Page 159: ...ounting Interrupt Request Generation Timing Timer underflow TAiIN Pin Function I O port or gate input TAiOUT Pin Function I O port or pulse output Read from Timer Count value can be read by reading TA...

Page 160: ...rmal port pin 1 Pulse is output 1 TAiOUT pin is a pulse output pin Pulse Output Function Select Bit MR2 RW b4 b3 0 0 Gate function not available 0 1 TAiIN pin functions as I O port 1 0 Counts w hile i...

Page 161: ...al signal or program When the timer overflows or underflows it reloads the reload register contents and continues counting When operating in free running mode the timer continues counting without relo...

Page 162: ...s falling edge of external signal 1 Counts rising edge of external signal Up Dow n Sw itching Factor Select Bit 0 UDF register 1 Input signal to TAiOUT pin 4 Count dow n w hen input on TAiOUT pin is l...

Page 163: ...Timer Count value can be read by reading Timer A2 A3 or A4 register Write to Timer When not counting and until the 1st count source is input after counting start Value written to TAi register is writt...

Page 164: ...ng 0 0 0 1 0 1 b3 Symbol TMOD1 TA2MR to TA4MR TCK1 bit is valid for Timer A3 mode register No matter how this bit is set Timer A2 and A4 alw ays operate in normal processing mode and x4 processing mod...

Page 165: ...be the rising or falling edge by using the POL bit in the INT2IC register The Z phase pulse width applied to the INT2 pin must be equal to or greater than one clock cycle of Timer A3 count source The...

Page 166: ...ollowing triggers occurs External trigger input from the TAiIN pin Timer B2 overflow or underflow Timer Aj j i 1 except j 4 if i 0 overflow or underflow Timer Ak k i 1 except k 0 if i 4 overflow or un...

Page 167: ...e Select Bit b7 b6 0 0 f1 or f2 4 0 1 f8 1 0 f32 1 1 fC32 TA0MR to TA4MR 0 1 0 Symbol b1 b0 1 0 One shot timer mode TMOD0 RW 0 Pulse is not output TAiOUT pin functions as I O port 1 Pulse is output 1...

Page 168: ...fC32 8 bit PWM High level width n m 1 fj n set value of TAi register high order address Cycle time 28 1 m 1 fj m set value of TAi register low order address Count Start Condition TAiS bit of TABSR re...

Page 169: ...b2 b1 b0 RW MR0 b1 b0 1 1 PWM mode 1 TMOD0 RW Pulse Output Function Select Bit 4 0 Pulse is not output TAiOUT pin functions as I O port 1 Pulse is output 1 TAiOUT pin functions as a pulse output pin...

Page 170: ...GH and TAiTGL bits 1 fj n Set to 0 upon accepting an interrupt request or by writing in program H L Count source 1 Input signal to TAiIN pin Underflow signal of 8 bit prescaler 2 PWM pulse output from...

Page 171: ...Timer B4 0353h 0352h Timer B3 Timer B5 0355h 0354h Timer B4 Select Clock Source 01 Event Counter 00 Timer 10 Pulse Period and Pulse Width Measurement Reload Register 8 low order bits 8 high order bits...

Page 172: ...Timer B5 Count Source Select Bit Function varies w ith each operation mode TCK1 RW TCK0 RW Timer Bi Register i 0 to 5 1 Symbol Address After Reset TB0 0391h 0390h Indeterminate TB1 0393h 0392h Indeter...

Page 173: ...er B3 B4 B5 Count Start Flag Address After Reset 0340h 000XXXXXb Bit Symbol Function RW b2 b1 RW RW b7 b6 b5 b4 b3 b0 Bit Name TBSR Symbol RW TB3S b4 b0 Timer B3 Count Start Flag Timer B4 Count Start...

Page 174: ...unt value can be read by reading TBi register Write to Timer When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload regi...

Page 175: ...or underflow j i 1 except j 2 if i 0 j 5 if i 3 Count Operation Down count When the timer underflows it reloads the reload register contents and continues counting Divide Ratio 1 n 1 n set value of T...

Page 176: ...indeterminate Has no effect in event counter mode Can be set to 0 or 1 Event Clock Select 0 Input from TBiIN pin 2 1 TBj overflow or underflow j i 1 how ever j 2 if i 0 j 5 if i 3 TCK1 RW 0 1 RW MR0...

Page 177: ...egister Table 15 8 Specifications in Pulse Period and Pulse Width Measurement Mode Item Specification Count Source f1 f2 f8 f32 fC32 Count Operation Up count Counter value is transferred to reload reg...

Page 178: ...edge and the next rising edge of measured pulse 1 0 Pulse w idth measurement Measurement betw een a falling edge and the next rising edge of measured pulse and betw een a rising edge and the next fall...

Page 179: ...bit 5 to bit 7 in the TABSR register Set to 0 upon accepting an interrupt request or by writing in program i 0 to 5 Measurement pulse H Count source Timing at which counter reaches 0000h 1 1 Transfer...

Page 180: ...phase waveform control Timer B2 used in the timer mode Carrier wave cycle control Dead time timer 3 eight bit timer and shared reload register Dead time control Output Waveform Triangular wave modulat...

Page 181: ...ut Signal V Phase Output Signal U Phase Output Signal U Phase Output Signal Trigger Trigger Trigger Trigger Three Phase Output Shift Register U Phase Trigger Trigger Timer A4 One Shot Pulse 1 0 INV00...

Page 182: ...in high impedance states Set the INV01 bit to 1 af ter setting the ICTB2 register The INV00 and INV01 bits are enabled only when the INV11 bit is set to 1 three phase mode 1 The ICTB2 counter is incre...

Page 183: ...6 bit is set to 0 Triangular w ave modulation mode and the INV11 bit to 1 three phase mode 1 If the follow ing conditions are all met set the INV16 bit to 1 rising edge of the three phase output shift...

Page 184: ...TA2 0389h to 0388h 038Bh to 038Ah Indeterminate TA4 038Fh to 038Eh Indeterminate TA11 TA21 0343h to 0342h 0345h to 0344h Indeterminate TA41 0347h to 0346h Indeterminate Setting Range RW NOTES 1 2 3 4...

Page 185: ...tooth wave modulation mode set this bit to 0 Timer B2 underflow Related pins are U P8_0 TA4OUT U __ P8_1 TA4IN V P7_2 CLK2 TA1OUT V __ P7_3 CTS2 RTS2 TA1IN Write to this register after setting the PRC...

Page 186: ...Symbol Address After Reset TRGSR 0383h 00h Bit Symbol Bit Name Function RW NOTES 1 2 Set the corresponding port direction bit to 0 input mode Overflow or underflow b7 b6 b5 b4 b3 b2 b1 b0 RW Timer A1...

Page 187: ...Function RW Bit Name TABSR Symbol b3 b2 b1 b0 b7 b6 b5 b4 RW RW RW TA3S TB1S RW TB0S 0 Stops counting 1 Starts counting RW RW RW RW Timer A4 Count Start Flag Timer B1 Count Start Flag Timer A2 Count...

Page 188: ...W Set to 0 w ith the three phase motor control timer function Pulse output Function Select Bit TMOD1 Operation Mode Select Bit b7 b6 b5 b4 b3 b2 b1 b0 RW RW MR1 External Trigger Select Bit MR2 Timer B...

Page 189: ...TA4 and TA41 registers are changed whenever Timer B2 interrupt is generated First time TA41 n TA4 n Second time TA41 p TA4 p Default value of the IDB0 and IDB1 registers DU0 1 DUB0 0 DU1 0 DUB1 1 They...

Page 190: ...ut Signal 1 U Phase Output Signal 1 U Phase U Phase INV14 0 L active U Phase U Phase INV14 1 H active Timer A4 Start Trigger Signal 1 Timer A4 One Shot Pulse 1 Dead time Rewrite the IDB0 and IDB1 regi...

Page 191: ...The M16C 62P 80 pin version and M16C 62PT 80 pin version do not include CLK2 CTS2 RTS2 and SIN pins Do not use the function which needs these pins Note The M16C 62P 80 pin version and M16C 62PT 80 pin...

Page 192: ...n UART transmission Clock synchronous type CKDIR 1 0 RXD polarity reversing circuit 1 0 RCSP 1 VSS 0 1 PCLK1 f1SIO or f2SIO 1 2 Main clock PLL clock or on chip oscillator clock 1 2 1 8 f8SIO f32SIO f1...

Page 193: ...ck synchronous type CKDIR RXD polarity reversing circuit 0 1 SMD2 to SMD0 010 100 101 110 001 010 100 101 110 001 0 1 RTS1 CTS1 Clock output pin select CTS1 RTS1 CTS0 CLKS1 VSS CRD 0 0 0 CRS 0 0 1 CLK...

Page 194: ...hronous type CKDIR 1 0 RXD polarity reversing circuit 1 0 VSS 0 1 SMD2 to SMD0 010 100 101 110 001 010 100 101 110 001 0 1 CRS CRD CTS2 RTS2 NOTES 1 UART2 is the N channel open drain output Cannot be...

Page 195: ...RT 9 bits Clock synchronous type UART 8 bits UART 9 bits UARTi receive register UiTB register UiRB register Data bus low order bits Data bus high order bits Logic reverse circuit MSB LSB conversion ci...

Page 196: ...bled all of the SUM PER FER and OER bits are set to 0 no error The SUM bit is set to 0 no error w hen all of the PER FER and OER bits 0 no error Also the PER and FER bits are set to 0 by reading the l...

Page 197: ...U1BRG 03A9h Indeterminate U2BRG 0379h Indeterminate Setting Range RW NOTES 1 2 3 b7 b0 Write to this register after setting the CLK1 to CLK0 bits in the UiC0 register Function Use MOV instruction to...

Page 198: ...0 0 0 0 Serial interface disabled 0 0 1 Clock synchronous serial I O mode 0 1 0 I2 C mode 3 1 0 0 UART mode transfer data 7 bits long 1 0 1 UART mode transfer data 8 bits long 1 1 0 UART mode transfer...

Page 199: ...ransfer Format Select Bit 3 UFORM RW TXD2 SDA2 and SCL2 are N channel open drain output Cannot be set to the CMOS output No NCH bit in U2C0 register is assigned When w rite set to 0 The UFORM bit is e...

Page 200: ...ble Bit 0 No reverse 1 Reverse 0 Output disabled 1 Output enabled UiERE RW UiLCH RW UART2 Transmit Receive Control Register 1 Address After Reset 037Dh 00000010b Bit Symbol Function RW NOTES 1 The U2L...

Page 201: ...Set to 0 0 No auto clear function 1 Auto clear at occurrence of bus collision Underflow signal of Timer A3 in UART0 underflow signal of Timer A4 in UART1 underflow signal of Timer A0 in UART2 RW SCLL...

Page 202: ...SMR3 to U2SMR3 Address b7 b6 b5 b4 b3 b2 b1 Bit Name Symbol Clock Phase Set Bit b4 b2 b0 CKPH Clock Output Select Bit Nothing is assigned When w rite set to 0 When read its content is indeterminate No...

Page 203: ...d 1 SCL L hold enabled STSPSEL 0 Start and stop conditions not output 1 Start and stop conditions output RW RW ACKD STPREQ b0 RSTAREQ STAREQ RW b7 b6 b5 b4 b3 b2 b1 U0SMR4 to U2SMR4 Bit Name Symbol Fu...

Page 204: ...E bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register 0 data present in UiTB register If CTS function is selected input on the CTSi pin L Reception Start Condition Before r...

Page 205: ...se TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function NCH Select TXDi pin output mode 2 CKPOL Select the transfer clock polarity UFORM Select the LSB first or MSB first U...

Page 206: ...if the CLKPOL bit 1 Table 17 3 Pin Functions when not select multiple transfer clock output pin function Pin Name Function Method of Selection TXDi i 0 to 2 P6_3 P6_7 P7_0 Serial Data Output Outputs...

Page 207: ...ransmit Timing when internal clock is selected The above timing diagram applies to the case where the register bits are set as follows CKDIR bit in UiMR register 0 internal clock CRD bit in UiC0 regis...

Page 208: ...RE bit in the UiC1 register transmission enabled regardless of the TE bit in the UiCi register 17 1 1 2 CLK Polarity Select Function Use the CKPOL bit in the UiC0 register i 0 to 2 to select the tran...

Page 209: ...2 1 continuous receive mode the TI bit in the UiC1 register is set to 0 data present in the UiTB register by reading the UiRB register In this case i e UiRRM bit 1 do not write dummy data to the UiTB...

Page 210: ...k for UART1 is an internal clock Figure 17 17 Transfer Clock Output from Multiple Pins D0 D1 D2 D3 D4 D5 D6 D7 Transfer Clock TXDi No Reverse H L H L TXDi Reverse D0 D1 D2 D3 D4 D5 D6 D7 H L 1 When Th...

Page 211: ...bit 0 CTS function is selected CTSi RTSi pin is CTS function CRD bit 0 CRS bit 1 RTS function is selected CTSi RTSi pin is RTS function 17 1 1 8 CTS RTS Separate Function UART0 This function separates...

Page 212: ...ction is selected input on the CTSi pin L Reception Start Condition Before reception can start meet the following requirements The RE bit in the UiC1 register 1 reception enabled Start bit detection I...

Page 213: ...ock or external clock STPS Select the stop bit PRY PRYE Select whether parity is included and whether odd or even IOPOL Select the TXD RXD input output polarity UiC0 CLK0 CLK1 Select the count source...

Page 214: ...tput H outputs when performing reception only RXDi P6_2 P6_6 P7_1 Serial Data Input PD6_2 bit and PD6_6 bit in the PD6 register 0 PD7_1 bit in the PD7 register 0 Can be used as an input port when perf...

Page 215: ...is set to 0 SP SP Start bit SP 1 8 bit Data Transmit Timing with a parity and 1 stop bit 1 9 bit Data Transmit Timing with no parity and 2 stop bits Stop bit Start bit Stop bit TC 16 n 1 fj or 16 n 1...

Page 216: ...00 f1 34 22h 28571 51 33h 28846 31250 f1 31 1Fh 31250 47 2Fh 31250 38400 f1 25 19h 38462 38 26h 38462 51200 f1 19 13h 50000 28 1Ch 51724 D0 Start bit Sampled L UiBRG count source RXDi Transfer clock R...

Page 217: ...register 17 1 2 3 LSB First MSB First Select Function As shown in Figure 17 21 use the UFORM bit in the UiC0 register to select the transfer format This function is valid when transfer data is 8 bits...

Page 218: ...UiC1 Register 0 No Reverse 2 When the UiLCH Bit 1 Reverse Transfer Clock H L NOTES 1 This applies to the case where the CKPOL bit in the UiC0 register 0 transmit data output at the falling edge of th...

Page 219: ...CTS function is selected CTSi RTSi pin is CTS function CRD bit 0 CRS bit 1 RTS function is selected CTSi RTSi pin is RTS function 17 1 2 7 CTS RTS Separate Function UART0 This function separates CTS0...

Page 220: ...bits Transfer Clock During master CKDIR bit in the UiMR i 0 to 2 register 0 internal clock fj 2 n 1 fj f1SIO f2SIO f8SIO f32SIO n Setting value of UiBRG register 00h to FFh During slave CKDIR bit 1 e...

Page 221: ...ICM2 0 S R Q ALS R S SWC IICM 1 and IICM2 0 IICM2 1 IICM2 1 SWC2 SDHI DMA0 DMA1 request UART1 DMA0 only Noise Filter i 0 to 2 IICM Bit in UiSMR register IICM2 SWC ALS SWC2 SDHI Bit in UiSMR2 register...

Page 222: ...D 1 TXEPT Transmit buffer empty flag Transmit buffer empty flag CRD 4 Set to 1 Set to 1 NCH Set to 1 2 Set to 1 2 CKPOL Set to 0 Set to 0 UFORM Set to 1 Set to 1 UiC1 TE Set this bit to 1 to enable tr...

Page 223: ...dition Set to 0 RSTAREQ Set this bit to 1 to generate restart condition Set to 0 STPREQ Set this bit to 1 to generate stop condition Set to 0 STSPSEL Set this bit to 1 to output each condition Set to...

Page 224: ...RS No acknowledgment detection NACK Rising edge of SCLi 9th bit UARTi transmission Rising edge of SCLi 9th bit UARTi transmission Falling edge of SCLi next to the 9th bit Factor of Interrupt Number 16...

Page 225: ...CK D8 ACK NACK D6 D5 D4 D3 D2 D1 D8 ACK NACK D7 SDAi SCLi D0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15 b9 b8 b7 b0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB register b15 b9 b8...

Page 226: ...f Start and Stop Condition 17 1 3 2 Output of Start and Stop Condition A start condition is generated by setting the STAREQ bit in the UiSMR4 register i 0 to 2 to 1 start A restart condition is genera...

Page 227: ...factors arbitration lost to occur in which case the SDAi pin is placed in the high impedance state at the same time the ABT bit is set to 1 unmatching detected Table 17 14 STSPSEL Bit Functions Funct...

Page 228: ...pin is fixed to low level output at the falling edge of the clock pulse next to the 9th Setting the SWC9 bit 0 SCL hold low disabled frees the SCLi pin from low level output 17 1 3 5 SDA Output The da...

Page 229: ...pplied However the UARTi output value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock The rec...

Page 230: ...of UiBRG register 00h to FFh Slave mode CKDIR bit 1 external clock selected Input from CLKi pin Transmit Receive Control Controlled by input output ports Transmission Start Condition Before transmissi...

Page 231: ...J09B0185 0241 Figure 17 29 Serial Bus Communication Control Example UART2 P1_3 P1_2 P7_0 TXD2 P7_2 CLK2 P7_1 RXD2 P9_3 P7_0 TXD2 P7_2 CLK2 P7_1 RXD2 P9_3 P7_0 TXD2 P7_2 CLK2 P7_1 RXD2 Microcomputer Ma...

Page 232: ...for master mode or 1 for slave mode IOPOL Set to 0 UiC0 CLK1 CLK0 Select the count source for the UiBRG register CRS Invalid because CRD 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Select T...

Page 233: ...nicated Figure 17 30 shows the Transmission and Reception Timing in Master Mode Internal Clock Figure 17 31 shows the Transmission and Reception Timing CKPH 0 in Slave Mode External Clock while Figure...

Page 234: ...ut CKPOL 0 CKPH 0 Clock input CKPOL 1 CKPH 0 Data output timing 1 Data input timing H L H L H L H L D0 D1 D2 D3 D4 D6 D7 D5 Indeterminate NOTES 1 UART2 output is an N channel open drain and must be pu...

Page 235: ...Bit Function UiTB 0 to 8 Set transmission data UiRB 3 0 to 8 Reception data can be read OER FER PER SUM Error flag UiBRG 0 to 7 Set a bit rate UiMR SMD2 to SMD0 Set to 110b CKDIR Select the internal c...

Page 236: ...lision is determined when timer Aj one shot timer mode underflows TXDi RXDi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP i 0 to 2 Timer Aj Timer A...

Page 237: ...alue of U2BRG register 00h to FFh CKDIR bit 1 external clock fEXT 16 n 1 fEXT Input from CLK2 pin n Setting value of U2BRG register 00h to FFh Transmission Start Condition Before transmission can star...

Page 238: ...PRY Set this bit to 1 for direct format or 0 for inverse format PRYE Set to 1 IOPOL Set to 0 U2C0 CLK1 CLK0 Select the count source for the U2BRG register CRS Invalid because CRD 1 TXEPT Transmit reg...

Page 239: ...rce f1SIO f2SIO f8SIO f32SIO fEXT frequency of U2BRG count source external clock n value set to U2BRG The above timing diagram applies to the case where data is transferred in the direct format STPS b...

Page 240: ...s returned high When transmitting a transmission finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit Therefore whether a parit...

Page 241: ...determines whether a parity error occurs When inverse format set the PRYE bit to 1 the PRY bit to 0 the UFORM bit to 1 and the U2LCH bit to 1 When data are transmitted values set in the U2TB register...

Page 242: ...iagram Data bus SI Oi interrupt request NOTES 1 i 3 4 n A value set in the SiBRG register SiTRR register SI O counter i 8 SMi5 LSB MSB SMi2 SMi3 SMi3 SMi6 SMi1 to SMi0 CLKi SOUTi SINi SiBRG register S...

Page 243: ...1 1 Do not set to this value 0 Input output port 1 SOUTi output CLKi function RW 0 LSB first 1 MSB first RW 0 Transmit data is output at falling edge of transfer clock and receive data is input at ri...

Page 244: ...divides the count source by n 1 00h to FFh Write to this register w hile serial interface is neither transmitting nor receiving b0 b7 SI Oi Bit Transmit Receive Register i 3 4 1 2 Symbol Address Afte...

Page 245: ...internal clock the transfer clock stops in the high state if the SMi4 bit 0 or stops in the low state if the SMi4 bit 1 Table 17 20 SI O3 and SI O4 Specifications Item Specification Transfer Data Form...

Page 246: ...data input at the rising edge of the transfer clock SMi5 0 LSB first and SMi6 1 internal clock 2 When the SMi6 bit 1 internal clock the SOUTi pin is placed in the high impedance state after the trans...

Page 247: ...Initial Value 1 NOTES 1 This diagram applies to the case where the bits in the SiC register are set as follows SMi2 0 SOUTi output SMi5 0 LSB first and SMi6 0 external clock 2 SOUTi can only be initi...

Page 248: ...AN2_7 as analog input pins Table 18 1 Performance of A D Converter Item Performance Method of A D Conversion Successive approximation capacitive coupling amplifier Analog input Voltage 1 0V to AVCC V...

Page 249: ...AN2_4 AN2_5 AN2_6 AN2_7 PM01 to PM00 00b ADGSEL1 to ADGSEL0 11b OPA1 to OPA0 11b PM01 to PM00 00b ADGSEL1 to ADGSEL0 11b OPA1 to OPA0 00b fAD 1 3 CKS2 1 2 1 2 AD A D conversion rate selection Resisto...

Page 250: ...MD0 0 A D conversion disabled 1 A D conversion started CKS0 TRG Trigger Select Bit RW A D Control Register 1 1 Symbol Address After Reset ADCON1 03D7h 00h Symbol Address After Reset RW NOTES 1 2 0 Vr...

Page 251: ...ents are 0 0 After Reset 00h CKS1 The AD frequency must be 12 MHz or less The selected AD frequency is determined by a combination of the CKS0 bit in the ADCON0 register the CKS1 bit in the ADCON1 reg...

Page 252: ...When read the content is indeterminate Nothing is assigned When w rite set to 0 When read their contents are 0 Address 03C1h to 03C0h 03C3h to 03C2h 03C5h to 03C4h 03C7h to 03C6h 03C9h to 03C8h 03CBh...

Page 253: ...in Analog voltage applied to the pin is converted to a digital code once A D Conversion Start Condition When the TRG bit in the ADCON0 register is 0 software trigger The ADST bit in the ADCON0 registe...

Page 254: ...se the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin How ever if VCC2 VCC1 do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins Frequency Select Bit 0 Refer to...

Page 255: ...its in the ADCON1 register select a pin Analog voltage applied to this pin is repeatedly converted to a digital code A D Conversion Start Condition When the TRG bit in the ADCON0 register is 0 softwar...

Page 256: ...alog Input Pin Select Bit 2 3 0 A D conversion disabled 1 A D conversion started b2 b1 b0 0 0 0 AN0 is selected 0 0 1 AN1 is selected 0 1 0 AN2 is selected 0 1 1 AN3 is selected 1 0 0 AN4 is selected...

Page 257: ...CON2 register select pins Analog voltage applied to this pins is converted one by one to a digital code A D Conversion Start Condition When the TRG bit in the ADCON0 register is 0 software trigger The...

Page 258: ...N2_7 can be used in the same w ay as AN0 to AN7 Use the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin How ever if VCC2 VCC1 do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as a...

Page 259: ...CON1 register and the ADGSEL1 to ADGSEL0 bits in the ADCON2 register select pins Analog voltage applied to the pins is repeatedly converted to a digital code A D Conversion Start Condition When the TR...

Page 260: ...0 bits in the ADCON2 register to select the desired pin How ever if VCC2 VCC1 do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins If the VCUT bit is reset from 0 Vref unconnected to 1 Vr...

Page 261: ...with priority given to pins selected by the SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits Example If AN0 selected input voltages are A D converted in order of AN0 AN1 AN0 AN2...

Page 262: ..._7 and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7 Use the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin How ever if VCC2 VCC1 do not use AN0_0 to AN0_7 and AN...

Page 263: ...The A D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers respectively 18 2 4 18 2 4 External Operation Amplifier Op Amp Connection Mode Multiple analog inputs can b...

Page 264: ...ensor equivalent circuit be R0 internal resistance of microcomputer be R precision error of the A D converter be X and the resolution of A D converter be Y Y is 1024 in the 10 bit mode and 256 in the...

Page 265: ...of 390 REJ09B0185 0241 Figure 18 11 Analog Input Pin and External Sensor Equivalent Circuit R0 R 7 8k C 1 5pF VIN VC Sampling time 3 AD Sample and hold enabled 2 AD Sample and hold disabled Microcomp...

Page 266: ...the corresponding port Output analog voltage V is determined by a set value n decimal in the DAi register V VREF X n 256 n 0 to 255 VREF reference voltage Table 19 1 lists the D A Converter Performanc...

Page 267: ...RW NOTES 1 b3 b2 b1 b0 b7 b6 b5 b4 When not using the D A converter clear the DAiE bit i 0 to 1 to 0 output disabled to reduce the unnecessary current consumption in the chip and set the DAi register...

Page 268: ...the CRC Circuit Block Diagram Figure 20 2 shows the CRC related Registers Figure 20 3 shows the Calculation Example using the CRC Operation Figure 20 1 CRC Circuit Block Diagram Figure 20 2 CRCD and...

Page 269: ...on As shown in 3 above bit position of 01h 00000001b written to the CRCIN register is inversed and becomes 10000000b Add 1000 0000 0000 0000 0000 0000b as 10000000b plus 16 digits to 0000 0000 0000 00...

Page 270: ...t When using any pin as a bus control pin refer to 8 2 Bus Control P0 to P5 P12 and P13 are capable of VCC2 level input output P6 to P11 and P14 are capable of VCC1 level input output NOTES 1 There is...

Page 271: ...g Pi register and data can be written to the port latch by writing to the Pi register The data written to the port latch is output from the pin The bits in the Pi register correspond one for one to ea...

Page 272: ...Data bus Data bus Data bus Pull up selection Direction register Direction register Direction register Direction register Port latch Port latch Port latch Port latch Pull up selection Pull up selection...

Page 273: ...r the port P0 to P5 and P12 to P13 P8_2 to P8_4 Data bus Pull up selection Direction register Port latch Input to respective peripheral functions NOTE 1 P6_1 P6_5 P7_2 1 Output Data bus Direction regi...

Page 274: ...espective peripheral functions Output 1 P8_5 Data bus NMI interrupt input P6_3 P6_7 Output 1 Data bus Pull up selection Direction register Port latch Switching between CMOS and Nch Switching between C...

Page 275: ...output 1 Output Direction register Direction register Direction register Data bus Data bus Data bus Port latch Port latch Port latch Analog input Analog input Pull up selection Pull up selection Pull...

Page 276: ...selection Port latch Data bus NOTE 1 NOTE 1 NOTES 1 Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC VCC VCC1 for the port P6 to P11 and P14 and VCC2 for the...

Page 277: ...PD4 to PD7 03E2h 03E3h 03E6h 03E7h RW PDi_3 RW PDi_2 b7 b6 b5 b4 b3 b2 b1 b0 RW 0 Input mode Functions as an input port 1 Output mode Functions as an output port i 0 to 7 and 9 to 13 Port Pi_0 Direct...

Page 278: ...is high impedance Pi_6 RW Pi_5 Port Pi_6 Bit Port Pi_5 Bit RW Pi_4 RW RW Pi_3 RW Symbol P0 to P3 P4 to P7 Pi_2 Address 03E0h 03E1h 03E4h 03E5h 03E8h 03E9h 03ECh 03EDh Pi_1 RW b3 b2 b1 b0 03F9h RW Fun...

Page 279: ...ull UP P13_4 to P13_7 Pull UP RW RW 0 Unusable 2 1 Usable Port P14 Control Register 128 Pin Package After Reset XX00XXXXb Bit Symbol RW Nothing is assigned When w rite set to 0 When read their content...

Page 280: ...ents of these bits can be modified The values after hardw are reset 1 and low voltage detection reset hardw are reset 2 are as follow s 00000000b w hen input on CNVSS pin is L 00000010b w hen input on...

Page 281: ...this bit is 1 pulled high and the direction bit is 0 input mode is pulled high PU20 b7 b6 b5 b4 RW b3 b2 b1 b7 b6 P8_0 to P8_3 Pull Up P8_4 to P8_7 Pull Up 2 P9_0 to P9_3 Pull Up RW PU24 RW RW PU23 Po...

Page 282: ...P7_0 and P7_1 are set for output mode make sure a low level signal is output from the pins The ports P7_0 and P7_1 are N channel open drain outputs 4 With external clock input to XIN pin 5 Process th...

Page 283: ...input ports 4 When the ports P7_0 and P7_1 are set for output mode make sure a low level signal is output from the pins The ports P7_0 and P7_1 are N channel open drain outputs 5 With external clock i...

Page 284: ...essor mode HOLD RDY ALE BCLK 1 BHE HLDA Open Open Open Port P4_5 CS1 to P4_7 CS3 NOTES 1 If the PM07 bit in the PM0 register is set to 1 BCLK not output connect this pin to VCC2 via a resistor pulled...

Page 285: ...es are defined to be per block erasure times For example assume a case where a 4 Kbyte block A is programmed in 2 048 operations by writing one word at a time and erased thereafter In this case the bl...

Page 286: ...Mbyte mode the extended accessible area 40000h to BFFFFh cannot be used Table 22 2 Flash Memory Rewrite Modes Overview Flash Memory Rewrite Mode CPU rewrite Mode 1 Standard Serial I O Mode Parallel I...

Page 287: ...Mode A program in the user ROM area is executed after a hardware reset occurs while an L signal is applied to the CNVSS pin However the boot ROM area cannot be read Figure 22 1 Flash Memory Block Dia...

Page 288: ...ewriting 22 2 1 ROM Code Protect Function The ROM code protect function inhibits the flash memory from being read or rewritten during parallel input output mode Figure 22 2 shows the ROMCP Register Th...

Page 289: ...mode Set the bit 5 to bit 0 to 111111b w hen the ROMCP1 bit is set to a value other than 11b If the bit 5 to bit 0 are set to values other than 111111b the ROM code protection may not become active by...

Page 290: ...od Memory expansion mode Boot mode Single chip mode Space where the rewrite control program can be placed User ROM area Boot ROM area User ROM area Space where the rewrite control program can be execu...

Page 291: ...CPU halts all program execution until the operation is completed or erase suspend is requested 22 3 3 Flash memory Control Register FIDR FMR0 and FMR1 registers Figure 22 4 to Figure 22 6 show the FI...

Page 292: ...ng the Clear Status command RO 0 Disables CPU rew rite mode 1 Enables CPU rew rite mode CPU Rew rite Mode Select Bit 1 Erase Status Flag 4 0 Terminated normally 1 Terminated in error RW RW RW RW User...

Page 293: ...etting the FMR01 bit to 0 Reserved Bit Set to 0 RO RW Set to 0 RO 0 EW0 mode 1 EW1 mode EW1 Mode Select Bit 1 b7 b0 RO The value in this bit w hen read is indeterminate b3 b2 b5 b4 RW Lock Bit Status...

Page 294: ...the flash memory Access to the flash memory is disabled when the FMSTP bit is set to 1 Set the FMSTP bit by program in a space other than the flash memory Set the FMSTP bit to 1 if one of the followin...

Page 295: ...s set to 0 For details refer to 22 3 8 Full Status Check Figure 22 7 shows Setting and Resetting of EW0 Mode Figure 22 8 show Setting and Resetting of EW1 Mode 22 3 3 8 FMR11 Bit EW0 mode is entered b...

Page 296: ...ter writing 0 2 Jump to a desired address in the flash memory NOTES 1 In CPU rewrite mode set the CM06 bit in the CM0 register and CM17 to 6 bits in the CM1 register to CPU clock frequency of 10 0 MHz...

Page 297: ...memory expansion or boot mode 2 In CPU rewrite mode set the CM06 bit in the CM0 register and the CM17 to 6 bits in the CM1 register to CPU clock frequency of 10 0 MHz or less Set the PM17 bit in the P...

Page 298: ...wer consumption mode or on chip oscillator low power consumption mode program Set the FMR01 bit to 0 CPU rewrite mode disabled Set the FMR01 bit to 1 after setting it to 0 CPU rewrite mode enabled Jum...

Page 299: ...interrupts with vectors in the relocatable vector table or address match interrupt during the auto program or auto erase period Do not use the watchdog timer interrupt The NMI interrupt is available...

Page 300: ...the WAIT instruction 22 3 4 11 Stop Mode When entering stop mode the following settings are required Set the FMR01 bit to 0 CPU rewrite mode disabled Disable DMA transfer before setting the CM10 bit t...

Page 301: ...after the next bus cycle The microcomputer remains in read array mode until another command is written Therefore contents from multiple addresses can be read consecutively 22 3 5 2 Read Status Regist...

Page 302: ...ot be altered or rewritten Figure 22 10 shows a Flow Chart of the Program Command Programming The lock bit protects each block from being programmed inadvertently Refer to 22 3 6 Data Protect Function...

Page 303: ...this command on the block where the rewrite control program is allocated In EW0 mode the microcomputer enters read status register mode as soon as an auto erase operation starts The status register c...

Page 304: ...an auto erase operation is completed The microcomputer remains in read status register mode until the read array command or read lock bit status command is written Only blocks 0 to 12 can be erased b...

Page 305: ...bit in the FMR1 register stores information on whether or not the lock bit of a specified block is locked Read the FMR16 bit after the FMR00 bit in the FMR0 register is set to 1 ready Figure 22 13 sho...

Page 306: ...ommand is executed while the FMR02 bit is set to 1 the target block or all blocks are erased regardless of lock bit status The lock bit status of each block are set to 1 after an erase operation is co...

Page 307: ...s set to 1 the program block erase erase all unlocked block and lock bit program commands are not accepted Table 22 5 Status Register Bits in Status Register Bit in FMR0 Register Status name Definitio...

Page 308: ...ock bit disabled no error occurs even under the conditions above Table 22 6 Errors and FMR0 Register State FMR00 Register Status Register State Error Error Occurrence Conditions FMR07 bit SR5 bit FMR0...

Page 309: ...P rogram error N O F ull sta tus checkcom plete d 1 E xe cu te the clear status register com m and and set the S R 4 bit to 0 com ple ted as expected 2 E xe cu te the read lock bit status com m and a...

Page 310: ...the serial programmer contact your serial programmer manufacturer Refer to the user s manual included with your serial programmer for instructions Table 22 7 lists Pin Functions Flash Memory Standard...

Page 311: ...Input Port P1 I VCC2 Input H or L level signal or open P2_0 to P2_7 Input Port P2 I VCC2 Input H or L level signal or open P3_0 to P3_7 Input Port P3 I VCC2 Input H or L level signal or open P4_0 to P...

Page 312: ...9 100 101 102 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 104 105 106 107 108 31 32 33 34...

Page 313: ...0 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Connect oscillato...

Page 314: ...0 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 CNVSS VCC1 EPM VS...

Page 315: ...29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 56 CNVSS VSS VCC1 TXD RXD SCLK BUSY RESET CE EP...

Page 316: ...CE P5_5 EPM RESET Reset input User reset signal Microcomputer NOTES 1 Control pins and external circuitry will vary according to programmer For more information see the programmer manual 2 In this ex...

Page 317: ...nitor output TXD output Microcomputer NOTES 1 In this example modes are switched between single chip mode and standard serial input output mode by controlling the CNVSS input with a switch P6_4 RTS1 P...

Page 318: ...e block operation in the boot ROM area is applied to only one 4 Kbyte block The rewrite control program in standard serial I O mode is written in the boot ROM area before shipment Do not rewrite the b...

Page 319: ...to P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P14_0 P14_1 VREF XIN 0 3 to VCC1 0 3 1 V P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P12_0 to P12_7 P13_0 to P13_7...

Page 320: ...o P2_7 P3_0 data input during memory expansion and microprocessor mode 0 5VCC2 VCC2 V P6_0 to P6_7 P7_2 to P7_7 P8_0 to P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P14_0 P14_1 XIN RESET CNVSS BYTE...

Page 321: ...44 MHz f XCIN Sub Clock Oscillation Frequency 32 768 50 kHz f Ring On chip Oscillation Frequency 0 5 1 2 MHz f PLL PLL Clock Oscillation Frequency 2 VCC1 3 0V to 5 5V 10 24 MHz VCC1 2 7V to 3 0V 10 46...

Page 322: ..._7 input AN2_0 to AN2_7 input ANEX0 ANEX1 input 3 LSB External operation amp connection mode 7 LSB VREF VCC1 3 3V AN0 to AN7 input AN0_0 to AN0_7 input AN2_0 to AN2_7 input ANEX0 ANEX1 input 5 LSB Ext...

Page 323: ...ed D A converter set to 00h The resistor ladder of the A D converter is not included Also when D A register contents are not 00h the IVREF will flow even if Vref id disconnected by the A D control reg...

Page 324: ...s important to track the total number of times erasure is used 9 Should erase error occur during block erase attempt to execute clear status register command then block erase command at least three ti...

Page 325: ...8V to 5 5V 3 3 3 8 4 4 V Vdet3 Reset Level Detection Voltage 1 2 2 2 2 8 3 6 V Vdet4 Vdet3 Electric potential difference of Low Voltage Detection and Reset Level Detection 0 3 V Vdet3s Low Voltage Re...

Page 326: ...terrupt for a Stop mode release or b Wait mode release CPU clock td R S a b td W S td R S STOP Release Time td W S Low Power Dissipation Mode Wait Mode Release Time td S R Vdet3r VCC1 CPU clock td S R...

Page 327: ...7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P12_0 to P12_7 P13_0 to P13_7 IOL 5mA 2 2 0 VOL LOW Output Voltage 3 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 to P9_7 P1...

Page 328: ...utput pins are open and other pins are VSS Mask ROM f BCLK 24MHz No division PLL operation 14 20 mA No division On chip oscillation 1 mA Flash Memory f BCLK 24MHz No division PLL operation 18 27 mA No...

Page 329: ...al Clock Input Cycle Time 62 5 ns tw H External Clock Input HIGH Pulse Width 25 ns tw L External Clock Input LOW Pulse Width 25 ns tr External Clock Rise Time 15 ns tf External Clock Fall Time 15 ns T...

Page 330: ...rd Unit Min Max tc TA TAiIN Input Cycle Time 200 ns tw TAH TAiIN Input HIGH Pulse Width 100 ns tw TAL TAiIN Input LOW Pulse Width 100 ns Table 23 18 Timer A Input External Trigger Input in Pulse Width...

Page 331: ...put Cycle Time 400 ns tw TBH TBiIN Input HIGH Pulse Width 200 ns tw TBL TBiIN Input LOW Pulse Width 200 ns Table 23 23 Timer B Input Pulse Width Measurement Mode Symbol Parameter Standard Unit Min Max...

Page 332: ...Symbol Parameter Standard Unit Min Max td BCLK AD Address Output Delay Time See Figure 23 2 25 ns th BCLK AD Address Output Hold Time in relation to BCLK 4 ns th RD AD Address Output Hold Time in rel...

Page 333: ...AD Address Output Delay Time See Figure 23 2 25 ns th BCLK AD Address Output Hold Time in relation to BCLK 4 ns th RD AD Address Output Hold Time in relation to RD 0 ns th WR AD Address Output Hold T...

Page 334: ...ime in relation to BCLK 4 ns th RD CS Chip Select Output Hold Time in relation to RD NOTE 1 ns th WR CS Chip Select Output Hold Time in relation to WR NOTE 1 ns td BCLK RD RD Signal Output Delay Time...

Page 335: ...tw TAL tc UP tw UPH tw UPL tc TB tw TBH tw TBL tc AD tw ADL th TIN UP tsu UP TIN TAiIN input When count on falling edge is selected TAiIN input When count on rising edge is selected TAiOUT input Up do...

Page 336: ...Characteristics Rev 2 41 Jan 10 2006 Page 321 of 390 REJ09B0185 0241 Figure 23 4 Timing Diagram 2 tsu D C CLKi TXDi RXDi tc CK tw CKH tw CKL tw INL tw INH INTi input td C Q th C D th C Q VCC1 VCC2 5V...

Page 337: ...0V Output timing voltage Determined with VOL 2 5V VOH 2 5V P0 P1 P2 P3 P4 P5_0 to P5_2 1 Common to setting with wait and setting without wait NOTES 1 These pins are set to high impedance regardless of...

Page 338: ...B Memory Expansion Mode Microprocessor Mode For setting with no wait Measuring conditions VCC1 VCC2 5V Input timing voltage VIL 0 8V VIH 2 0V Output timing voltage VOL 0 4V VOH 2 4V WR WRL WRH 25ns ma...

Page 339: ...25ns max ADi td BCLK AD 25ns max ALE 25ns max td BCLK ALE th BCLK ALE 4ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc th WR AD BHE td BCLK DB 40ns max 4ns min th BCLK DB td DB WR 0 5 tcyc 40 ns min...

Page 340: ...Hi Z tsu DB RD 40ns min th RD DB 0ns min th BCLK RD 0ns min th RD AD 0ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc Hi Z td BCLK CS 25ns max td BCLK AD 25ns max td BCLK ALE 25ns max th BCLK ALE 4...

Page 341: ...Hi Z tsu DB RD 40ns min th RD DB 0ns min th BCLK RD 0ns min th RD AD 0ns min th BCLK AD 4ns min th BCLK CS 4ns min Hi Z td BCLK CS 25ns max td BCLK AD 25ns max td BCLK ALE 25ns max th BCLK ALE 4ns mi...

Page 342: ...D 25ns max ALE 25ns max th BCLK ALE 4ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc th WR AD BHE td BCLK DB 40ns max 4ns min th BCLK DB td DB WR th WR DB ADi DBi Data output WR WRL WRH Write timing...

Page 343: ...th BCLK AD 4ns min td BCLK CS 25ns max td BCLK AD 25ns max th BCLK DB 4ns min th BCLK WR 0ns min th WR AD 0 5 tcyc 10 ns min th BCLK AD 4ns min th BCLK CS 4ns min td BCLK ALE 25ns max td BCLK WR 25ns...

Page 344: ...0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P12_0 to P12_7 P13_0 to P13_7 IOL 1mA 2 0 5 VOL LOW Output Voltage XOUT HIGHPOWER IOL 0 1mA 0 5 V LOWPOWER IOL 50 A 0 5 LOW Output Voltage XCOUT HIGHPOWER With no l...

Page 345: ...chip mode the output pins are open and other pins are VSS Mask ROM f BCLK 10MHz No division 8 11 mA No division On chip oscillation 1 mA Flash Memory f BCLK 10MHz No division 8 13 mA No division On ch...

Page 346: ...ut 1 Symbol Parameter Standard Unit Min Max tc External Clock Input Cycle Time NOTE 2 ns tw H External Clock Input HIGH Pulse Width NOTE 3 ns tw L External Clock Input LOW Pulse Width NOTE 3 ns tr Ext...

Page 347: ...ard Unit Min Max tc TA TAiIN Input Cycle Time 300 ns tw TAH TAiIN Input HIGH Pulse Width 150 ns tw TAL TAiIN Input LOW Pulse Width 150 ns Table 23 37 Timer A Input External Trigger Input in Pulse Widt...

Page 348: ...put Cycle Time 600 ns tw TBH TBiIN Input HIGH Pulse Width 300 ns tw TBL TBiIN Input LOW Pulse Width 300 ns Table 23 42 Timer B Input Pulse Width Measurement Mode Symbol Parameter Standard Unit Min Max...

Page 349: ...Symbol Parameter Standard Unit Min Max td BCLK AD Address Output Delay Time See Figure 23 12 30 ns th BCLK AD Address Output Hold Time in relation to BCLK 4 ns th RD AD Address Output Hold Time in re...

Page 350: ...AD Address Output Delay Time See Figure 23 12 30 ns th BCLK AD Address Output Hold Time in relation to BCLK 4 ns th RD AD Address Output Hold Time in relation to RD 0 ns th WR AD Address Output Hold T...

Page 351: ...Time in relation to BCLK 4 ns th RD CS Chip Select Output Hold Time in relation to RD NOTE 1 ns th WR CS Chip Select Output Hold Time in relation to WR NOTE 1 ns td BCLK RD RD Signal Output Delay Tim...

Page 352: ...tw TAL tc UP tw UPH tw UPL tc TB tw TBH tw TBL tc AD tw ADL th TIN UP tsu UP TIN TAiIN input When count on falling edge is selected TAiIN input When count on rising edge is selected TAiOUT input Up do...

Page 353: ...haracteristics Rev 2 41 Jan 10 2006 Page 338 of 390 REJ09B0185 0241 Figure 23 14 Timing Diagram 2 tsu D C CLKi TXDi RXDi tc CK tw CKH tw CKL tw INL tw INH INTi input td C Q th C D th C Q VCC1 VCC2 3V...

Page 354: ...4V Output timing voltage Determined with VOL 1 5V VOH 1 5V P0 P1 P2 P3 P4 P5_0 to P5_2 1 Common to setting with wait and setting without wait NOTES 1 These pins are set to high impedance regardless o...

Page 355: ...B Memory Expansion Mode Microprocessor Mode for setting with no wait Measuring conditions VCC1 VCC2 3V Input timing voltage VIL 0 6V VIH 2 4V Output timing voltage VOL 1 5V VOH 1 5V WR WRL WRH 30ns ma...

Page 356: ...30ns max ADi td BCLK AD 30ns max ALE 30ns max td BCLK ALE th BCLK ALE 4ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc th WR AD BHE td BCLK DB 40ns max 4ns min th BCLK DB td DB WR 0 5 tcyc 40 ns mi...

Page 357: ...x Hi Z tsu DB RD 50ns min th RD DB 0ns min th BCLK RD 0ns min th RD AD 0ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc Hi Z td BCLK CS 30ns max td BCLK AD 30ns max td BCLK ALE 30ns max th BCLK ALE...

Page 358: ...x Hi Z tsu DB RD 50ns min th RD DB 0ns min th BCLK RD 0ns min th RD AD 0ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc Hi Z td BCLK CS 30ns max td BCLK AD 30ns max td BCLK ALE 30ns max th BCLK ALE...

Page 359: ...ALE 40ns max th BCLK ALE 4ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc th WR AD BHE td BCLK DB 50ns max 4ns min th BCLK DB td DB WR th WR DB ADi DBi Data output WR WRL WRH Write timing Address 0...

Page 360: ...th BCLK AD 4ns min td BCLK CS 40ns max td BCLK AD 40ns max th BCLK DB 4ns min th BCLK WR 0ns min th WR AD 0 5 tcyc 10 ns min th BCLK AD 4ns min th BCLK CS 4ns min td BCLK ALE 40ns max td BCLK WR 40ns...

Page 361: ...7 P10_0 to P10_7 P11_0 to P11_7 P14_0 P14_1 VREF XIN 0 3 to VCC1 0 3 1 V P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P12_0 to P12_7 P13_0 to P13_7 0 3 to VCC2 0 3 1 V...

Page 362: ...0 P7_1 0 8VCC1 6 5 V VIL LOW Input Voltage 4 P3_1 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P12_0 to P12_7 P13_0 to P13_7 0 0 2VCC2 V P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 during single chip mode 0 0 2V...

Page 363: ...Symbol Parameter Measuring Condition Standard Unit Min Typ Max Resolution VREF VCC1 10 Bits INL Integral Non Linearity Error 10bit VREF VCC1 5V AN0 to AN7 input AN0_0 to AN0_7 input AN2_0 to AN2_7 inp...

Page 364: ...between block A and block 1 will also improve efficiency It is important to track the total number of times erasure is used 9 Should erase error occur during block erase attempt to execute clear stat...

Page 365: ...nal Power Supply Stabilization During Powering On VCC1 4 0V to 5 5V 2 ms td R S STOP Release Time 150 s td W S Low Power Dissipation Mode Wait Mode Release Time 150 s td P R VCC1 CPU clock CPU clock t...

Page 366: ..._0 to P4_7 P5_0 to P5_7 P12_0 to P12_7 P13_0 to P13_7 IOL 5mA 2 0 VOL LOW Output Voltage 2 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P14_0 P14_1 IOL 2...

Page 367: ...r pins are VSS Mask ROM f BCLK 24MHz No division PLL operation 14 20 mA No division On chip oscillation 1 mA Flash Memory f BCLK 24MHz No division PLL operation 18 27 mA No division On chip oscillatio...

Page 368: ...rsion 40 to 125 C V version unless otherwise specified Table 23 59 External Clock Input XIN input Symbol Parameter Standard Unit Min Max tc External Clock Input Cycle Time 62 5 ns tw H External Clock...

Page 369: ...ter Standard Unit Min Max tc TA TAiIN Input Cycle Time 200 ns tw TAH TAiIN Input HIGH Pulse Width 100 ns tw TAL TAiIN Input LOW Pulse Width 100 ns Table 23 63 Timer A Input External Trigger Input in P...

Page 370: ...B TBiIN Input Cycle Time 400 ns tw TBH TBiIN Input HIGH Pulse Width 200 ns tw TBL TBiIN Input LOW Pulse Width 200 ns Table 23 68 Timer B Input Pulse Width Measurement Mode Symbol Parameter Standard Un...

Page 371: ...f 390 REJ09B0185 0241 VCC1 VCC2 5V Switching Characteristics VCC1 VCC2 5V VSS 0V at Topr 40 to 85 C T version 40 to 125 C V version unless otherwise specified Figure 23 23 Ports P0 to P10 Measurement...

Page 372: ...tw TAL tc UP tw UPH tw UPL tc TB tw TBH tw TBL tc AD tw ADL th TIN UP tsu UP TIN TAiIN input When count on falling edge is selected TAiIN input When count on rising edge is selected TAiOUT input Up do...

Page 373: ...haracteristics Rev 2 41 Jan 10 2006 Page 358 of 390 REJ09B0185 0241 Figure 23 25 Timing Diagram 2 tsu D C CLKi TXDi RXDi tc CK tw CKH tw CKL tw INL tw INH INTi input td C Q th C D th C Q VCC1 VCC2 5V...

Page 374: ...A1 1 register TA11 0343 to 0342 Timer A2 1 register TA21 0345 to 0344 Timer A4 1 register TA41 0347 to 0346 Short circuit preventionTimer DTT 034C Timer B2 Interrupt Generating Frequency Set Counter...

Page 375: ...computer the power supply voltage applied to the VCC1 pin must meet the conditions of SVCC Figure 24 1 Timing of SVCC Symbol Parameter Standard Unit Min Typ Max SVCC Power supply rising gradient VCC1...

Page 376: ...6 Page 361 of 390 REJ09B0185 0241 24 3 Bus The ROMless version can operate only in the microprocessor mode connect the CNVSS pin to VCC1 When resetting CNVSS pin with H input contents of internal ROM...

Page 377: ...Parameter Standard Unit Min Typ Max f ripple Power supply ripple allowable frequency VCC1 10 kHz VP P ripple Power supply ripple allowable amplitude voltage VCC1 5V 0 5 V VCC1 3V 0 3 V VCC V T Power...

Page 378: ...ng wait mode Program Example JMP B L1 Insert JMP B instruction before WAIT instruction L1 FSET I WAIT Enter wait mode NOP More than 4 NOP instructions NOP NOP NOP When entering stop mode insert a JMP...

Page 379: ...r longer after setting the VCUT bit to 1 VREF connection D A converter When not performing D A conversion set the DAiE bit i 0 1 of DACON register to 0 input inhibited and DAi register to 00h Stopping...

Page 380: ...to any address and the PRC2 bit will be cleared to 0 write protected The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to 1 Make sure no inte...

Page 381: ...Especially when using NMI interrupt set a value in the ISP at the beginning of the program For the first and only the first instruction after reset all interrupts including NMI interrupt are disabled...

Page 382: ...s of the CPU operation clock If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are changed the IR bit may inadvertently set to 1 interrupt requested Be s...

Page 383: ...e sample program fragments Examples 1 through 3 show how to prevent the I flag from being set to 1 interrupts enabled before the interrupt control register is rewrited owing to the effects of the inte...

Page 384: ...to this bit it is set to 0 DMA not requested In order to prevent the DMAS bit from being modified to 0 1 should be written to the DMAS bit when 1 is written to the DMAE bit In this way the state of th...

Page 385: ...Timer A Event Counter Mode The timer remains idle after reset Set the mode count source counter value etc using the TAiMR i 0 to 4 register the TAi register the UDF register the ONSF register TAZIE TA...

Page 386: ...nting down once To generate a trigger while counting generate a second trigger between occurring the previous trigger and operating longer than one cycle of a timer count source If a low level signal...

Page 387: ...i 0 to 5 register before setting the TBiS bit in the TABSR or the TBSR register to 1 count starts Always make sure the TBiMR register is modified while the TBiS bit remains 0 count stops regardless wh...

Page 388: ...ing the clock synchronous serial I O operating a transmitter generates a shift clock Fix settings for transmission even when using the device only for reception Dummy data is output to the outside fro...

Page 389: ...IM Mode A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to 1 transmission complete and U2ERE bit to 1 error signal output after reset is deasserted Therefore when usin...

Page 390: ...de Also if the TGR bit in the ADCON0 register 1 external trigger make sure the port direction bit for the ADTRG pin is set to 0 input mode When using key input interrupts do not use any of the four AN...

Page 391: ...mode or repeat sweep mode 0 or 1 Use the main clock for CPU clock directly without dividing it If A D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register...

Page 392: ...tly depending on which side the programmable input output port or the peripheral function is currently selected When changing the PD14_i bit i 0 to 1 in the PC14 register from 0 input port to 1 output...

Page 393: ...rsion may have different characteristics operating margin noise tolerated dose noise width dose in electrical characteristics due to internal ROM different layout pattern etc When switching to the mas...

Page 394: ...he FMR01 bit to 0 CPU rewrite mode disabled before executing the WAIT instruction 24 15 4 Low power dissipation mode on chip oscillator low power dissipation mode If the CM05 bit is set to 1 main cloc...

Page 395: ...The address match interrupt cannot be used because the flash memory s internal data is referenced EW1 Mode Make sure that any interrupt which has a vector in the variable vector table or address match...

Page 396: ...Program Block Erase Erase All Unlock Blocks and Lock Bit Program Especially when the number of programming erasure times exceeds 1 000 the software command execution time is noticeably extended Theref...

Page 397: ...XSS pins and VCC2 and VSS pins using the shortest and thicker possible wiring Figure 24 5 shows the Bypass Capacitor Connection Figure 24 5 Bypass Capacitor Connection Bypass Capacitor Connecting Pat...

Page 398: ...he CM16 and CM17 bits in the CM1 register TN M16C 108 0309 Precaution 1 1 The CM05 bit in the CM0 register is set to 0 main clock oscillation and the CM02 bit is set to 1 peripheral function clock sto...

Page 399: ...CR2 register to 1 low voltage detection circuit enabled the D40 bit in the D4INT register to 1 low voltage detection interrupt enabled the D41 bit to 1 use low voltage detection interrupt to exit stop...

Page 400: ...09 0 145 0 20 0 10 0 75 0 75 0 20 0 125 1 0 P LQFP128 14x20 0 50 0 9g MASS Typ 128P6Q A PLQP0128KB A RENESAS Code JEITA Package Code Previous Code Terminal cross section c bp c 1 b1 e 0 8 0 5 0 825 0...

Page 401: ...5 0 20 0 25 0 09 0 145 0 20 0 08 1 0 1 0 0 18 0 125 1 0 Previous Code JEITA Package Code RENESAS Code PLQP0100KB A 100P6Q A FP 100U FP 100UV MASS Typ 0 6g P LQFP100 14x14 0 50 e 3 2 1 80 61 60 41 40 2...

Page 402: ...e System clock protective function Built in None protected by protect register Oscillation Stop Re oscillation Detection Function Built in None Low power consumption 18mA VCC1 VCC2 5V f BCLK 24MHz 8mA...

Page 403: ...un Error Generation Timing This error occurs if the serial I O started receiving the next data before reading the UiRB register i 0 to 2 and received the 7 th bit of the next data clock synchronous Th...

Page 404: ...tes x 3 32 Kbytes x1 64 Kbytes x 7 Flash memory max 512 Kbytes 7 blocks 8 Kbytes x 2 16 Kbytes x1 32 Kbytes x 1 64 Kbytes x 3 Flash memory max 256 Kbytes Program manner Word Page Program command softw...

Page 405: ...PRCR 105 PUR0 to PUR1 265 PUR2 266 PUR3 264 R RMAD0 to RMAD3 123 ROMCP 274 S S0RIC to S2RIC 111 S0TIC to S2TIC 111 S3BRG to S4BRG 229 S3C to S4C 228 S3IC to S4IC 112 S3TRR to S4TRR 229 SAR0 131 SAR1...

Page 406: ...n of 4 Mbyte Mode is partly revised 53 Notes 12 and 13 in Figure 1 9 2 is partly revised 54 Notes 2 and 5 in Figure 1 9 3 is partly revised 55 Figure 1 9 4 is partly revised 57 Note 4 in Figure 1 9 6...

Page 407: ...sed 130 Figure 1 16 1 is partly revised 132 Figure 1 16 3 is partly revised 134 Note 7 is added to TAi TAi1 Register in Figure 1 16 5 137 Figure 1 16 8 is partly revised 146 UiSMR2 Register in Figure...

Page 408: ...9 is partly revised 244 Note of Table 1 26 28 is partly revised 245 Figure 1 26 29 is partly revised 246 Measurement conditions of timing requirements are partly revised Table 1 26 30 is partly revis...

Page 409: ...ised 27 Table 1 5 2 is partly revised Table 1 5 3 is partly revised Explanation of 1 Limitations on Stop Mode is partly revised 28 Explanation of 1 Limitations on WAIT instruction is partly revised Fi...

Page 410: ...Timing is partly revised 109 TRGSR register of Figure 1 14 6 is partly revised 116 Table 1 14 4 is partly revised 117 Figure 1 14 12 is partly revised 129 Figure 1 16 2 is partly revised 130 Figure 1...

Page 411: ...WR DB and th WR AD in Figure 1 26 9 to 1 5 10 is partly revised 242 Note 2 is added to Table 1 26 29 247 Notes 1 and 2 in Table 1 26 45 is partly revised 248 Notes 1 in Table 1 26 46 is partly revised...

Page 412: ...oduct List is partly revised 11 Table 1 8 and Figure 1 4 are added 12 Table 1 9 and Figure 1 5 are added 13 16 Figure 1 6 to 1 9 ZP is added 17 Table 1 10 and 1 13 ZP is added to timer A 18 20 Table 1...

Page 413: ...le 15 2 is partly revised 131 15 1 2 1 Counter Initialization by Two Phase Pulse Signal Processing is partly revised 137 Note in 15 2 Timer B is added 140 Table 15 6 is partly revised 144 Note in 16 T...

Page 414: ...in Table 21 2 is added Note 7 in Table 21 3 is revised 242 273 Almost all pages are revised 22 Flash Memory Version 274 Table 23 1 is revised 275 Table 23 2 is revised 276 Table 23 3 is revised Note...

Page 415: ...24 10 A D Converter is partly revised 352 24 13 Mask ROM Version is added 356 24 15 Noise is added 357 25 Differences Depending on Manufacturing Period is a 2 40 Dec 15 2005 voltage down detection re...

Page 416: ...d 69 Table 8 8 Bit and Bus Cycle Related to Software 80 Figure 9 8 Relationship Between Address on 4 Mbyte ROM and Those on Microcomputer 2 is partly revised 89 Figure 10 7 Examples of Main Clock Conn...

Page 417: ...vised 201 17 1 2 1 Bit Rate is partly revised Table 17 9 Example of Bit Rates and Settings is partly revised 202 17 1 2 2 Counter Measure for Communication Error Occurs is partly revised 205 Table 17...

Page 418: ...e is partly revised Note 2 is partly revised Note 3 is added 297 300 Figures 22 15 to 22 18 are partly revised 301 Figure 22 19 Circuit Application in Standard I O Mode 1 is partly revised 302 Figure...

Page 419: ...ter is partly revised 377 24 12 Programable I O Ports is partly revised 379 24 15 2 Stop mode is partly revised 380 24 15 8 Operation speed is partly revised 381 24 15 14 Regarding Programming Erasing...

Page 420: ...Hardware Manual Publication Date Rev 2 41 Jan 10 2006 Published by Sales Strategic Planning Div Renesas Technology Corp 2006 Renesas Technology Corp All rights reserved Printed in Japan http www xinpi...

Page 421: ...2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan M16C 62P Group M16C 62P M16C 62PT Hardware Manual http www xinpian net IC 010 62245566 13810019655...

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