M16C/62P Group (M16C/62P, M16C/62PT)
14. DMAC
Rev.2.41
Jan 10, 2006
Page 136 of 390
REJ09B0185-0241
14.5
Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected
active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS
bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA requests are arbitrated
according to the channel priority, DMA0 > DMA1. The following describes DMAC operation when DMA0 and
DMA1 requests are detected active in the same sampling period. Figure 14.7 shows an example of DMA Transfer
by External Factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request are
generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is returned to the CPU. When
the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is completed, the bus
arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when DMA
requests, as DMA1 in Figure 14.7, occurs more than one time, the DMAS bit is set to “0” as soon as getting the bus
arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
Refer to
8.2.7 Hold Signal
for details about bus arbitration between the CPU and DMA.
Figure 14.7
DMA Transfer by External Factors
BCLK
DMA0
DMA1
DMA0
request bit
DMA1
request bit
CPU
INT0
INT1
Bus
arbitration
An example where DMA requests for external factors are detected active at the same
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