C - 4
REVISION HISTORY
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
271
Figure 1.27.7 is partly revised.
272
Explanation of “Interrupts” is partly revised.
Explanation of “Writing in the User ROM Space” is partly revised.
274
Table 1.27.4 is partly revised.
Explanation of “Read Array Command” is partly revised.
278
Explanation of “Program Command” is partly revised.
287
Figure 1.27.15 is partly revised.
293
Partly revised.
1.10
May 28, 2003
2
Table 1.1.1 is partly revised.
4-5
Table 1.1.2 and 1.1.3 is partly revised.
14-19 SFR is partly revised.
Note 1 is partly revised.
20
Explanation of “Hardware Reset 1” is partly revised.
23
Note 1 is added.
24
Figure 1.5.4 is partly revised.
Note 1 of Figure 1.5.5 is partly revised.
26
Figure 1.5.7 is partly revised.
27
Table 1.5.2 is partly revised.
Table 1.5.3 is partly revised.
Explanation of “1. Limitations on Stop Mode” is partly revised.
28
Explanation of “1. Limitations on WAIT instruction” is partly revised.
Figure 1.5.8 is partly revised.
31
Note is added.
33
Explanation of “Multiplexed Bus” is revised.
34
Explanation of “(2) Data Bus” is revised.
38
Explanation of “(7) Hold Signal” is revised.
Note 3 of Table 1.7.4 is added.
39
Note 4 of Table 1.7.5 is added.
40
Explanation of “(10) Software Wait” is revised.
41
Table 1.7.7 is revised.
46
Table of Figure 1.8.5 is revised.
47
Explanation is revised.
48-50 Figures 1.8.7 to 1.8.9 is partly revised.
51
Explanation of “Clock Generation Circuit” is revised.
52
Figure 1.9.1 is revised.
53
Note of Figure 1.9.2 is revised.
55
Note 12 is added.
58
Explanation of “(1) Main clock” is partly revised.
60
Explanation of “(4) PLL Clock” is partly revised.
Rev.
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