Renesas M16C/62P Group, Hardware Manual

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M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface
Rev.2.41 Jan 10, 2006 Page 202 of 390
REJ09B0185-0241
17.1.2.2 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below.
•
Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
•
Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register “000b” (Serial interface disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register “001b”, “101b”, “110b”.
(3) “1” is written to RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in the UiCi
register
17.1.2.3 LSB First/MSB First Select Function
As shown in Figure 17.21, use the UFORM bit in the UiC0 register to select the transfer format. This function is
valid when transfer data is 8 bits long.
Figure 17.21 Transfer Format
(1) When the UFORM Bit in the UiC0 Register = 0 (LSB First)
(2) When the UFORM Bit = 1 (MSB First)
NOTES :
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiLCH bit in the UiC1
register = 0 (no reverse), the STPS bit in the UiMR register = 0
(1 stop bit) and the PRYE bit in the UiMR register = 1 (parity enabled).
D1 D2 D3 D4 D5 D6 SP D0
D1 D2 D3 D4 D5 D6 SP D0
TXDi
RXDi
CLK
i
D6 D5 D4 D3 D2 D1 D0 D7
TXDi
RXDi
CLK
i
ST
ST
D7 P
D7 P
SP
SP
ST
ST
P
P
D6 D5 D4 D3 D2 D1 D0 D7
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
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