M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Rev.2.41
Jan 10, 2006
Page 164 of 390
REJ09B0185-0241
Figure 15.22
Operation Timing when Measuring a Pulse Period
Figure 15.23
Operation Timing when Measuring a Pulse Width
Count source
Measurement pulse
TBiS bit
IR bit in TBiIC
register
Timing at which counter
reaches “0000h”
“H”
“1”
Transfer
(indeterminate value)
“L”
“0”
“0”
MR3 bit in TBiMR
register
“1”
“0”
NOTES :
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “00b” (measure the
interval from falling edge to falling edge of the measurement pulse).
(NOTE 1)
(NOTE 1)
(NOTE 2)
Transfer
(measured value)
“1”
Reload register counter
transfer timing
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits
are assigned to the bit 5 to bit 7 in the TABSR register.
Set to “0” upon accepting an interrupt request or by writing in
program
i = 0 to 5
Measurement pulse
“H”
Count source
Timing at which counter
reaches “0000h”
“1”
“1”
Transfer
(measured value)
Transfer
(measured value)
“L”
“0”
“0”
“1”
“0”
(NOTE 1)
(NOTE 1)
(NOTE 1)
Transfer
(measured
value)
(NOTE 2)
Transfer
(indeterminate
value)
Reload register counter
transfer timing
TBiS bit
IR bit in TBiIC
register
MR3 bit in TBiMR
register
NOTES :
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “10b” (measure the
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TABSR register.
Set to “0” upon accepting an interrupt request or by
writing in program
i = 0 to 5
(NOTE 1)
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