M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
Rev.2.41
Jan 10, 2006
Page 209 of 390
REJ09B0185-0241
NOTES:
1.
If the source or factor of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to
24.7 Interrupt
)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to “0” (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
2.
Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled).
3.
Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
4.
First data transfer to UiRB register (Falling edge of SCLi 9th bit)
5.
See
Figure 17.28 STSPSEL Bit Functions
.
6.
See
Figure 17.26 Transfer to UiRB Register and Interrupt Timing
.
7.
When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (factor of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR27 bit to “1” (factor of interrupt: UART1 bus collision).
i = 0 to 2
Table 17.13
I
2
C Mode Functions
Function
Clock Synchronous Serial I/O
Mode (SMD2 to SMD0 = 001b,
IICM = 0)
I
2
C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
Factor of Interrupt Number
6, 7 and 10
(1, 5, 7)
−
Start condition detection or stop condition detection
(See
Table 17.14
STSPSEL Bit Functions
)
Factor of Interrupt Number
15, 17 and 19
(1, 6)
UARTi transmission
Transmission started or
completed (selected by UiIRS)
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
UARTi transmission
Rising edge of SCLi
9th bit
UARTi transmission
Falling edge of SCLi
next to the 9th bit
Factor of Interrupt Number
16, 18 and 20
(1, 6)
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Acknowledgment detection (ACK)
Rising edge of SCLi 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Timing for Transferring Data
From the UART Reception
Shift Register to the UiRB
Register
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Rising edge of SCLi 9th bit
Falling edge of SCLi
9th bit
Falling and rising
edges of SCLi 9th
bit
UARTi Transmission Output
Delay
Not delayed
Delayed
Functions of P6_3, P6_7 and
P7_0 Pins
TXDi output
SDAi input/output
Functions of P6_2, P6_6 and
P7_1 Pins
RXDi input
SCLi input/output
Functions of P6_1, P6_5 and
P7_2 Pins
CLKi input or output selected
−
(Cannot be used in I
2
C mode)
Noise Filter Width
15ns
200ns
Read RXDi and SCLi Pin
Levels
Possible when the corresponding
port direction bit = 0
Always possible no matter how the corresponding port direction bit is set
Initial Value of TXDi and
SDAi Outputs
CKPOL = 0 (H)
CKPOL = 1 (L)
The value set in the port register before setting I
2
C mode
(2)
Initial and End Values of SCLi
−
H
L
H
L
DMA1 Factor
(6)
UARTi reception
Acknowledgment detection (ACK)
UARTi reception
Falling edge of SCLi 9th bit
Store Received Data
1st to 8th bits of the received data
are stored into bits 7 to 0 in the
UiRB register
1st to 8th bits of the received data are
stored into bits 7 to 0 in the UiRB
register
1st to 7th bits of the received data are
stored into bits 6 to 0 in the UiRB register.
8th bit is stored into bit 8 in the UiRB
register.
1st to 8th bits are
stored into bits 7 to
0 in the UiRB
register
(3)
Read Received Data
The UiRB register status is read
Bits 6 to 0 in the
UiRB register
(4)
are
read as bits 7 to 1.
Bit 8 in the UiRB
register is read as
bit 0.
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