M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
Rev.2.41
Jan 10, 2006
Page 92 of 390
REJ09B0185-0241
Figure 10.9
Procedure to Use PLL Clock as CPU Clock Source
Using the PLL clock as the clock source for the CPU
Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits
to “00b” (main clock undivided), and the CM06 bit to “0”
(CM16 and CM17 bits enabled).
(1)
Set the PLC02 to PLC00 bits (multiplying factor).
(When PLL clock > 16MHz)
Set the PM20 bit to “0” (2 wait states).
Set the PLC07 bit to “1” (PLL operation).
Wait until the PLL clock becomes stable (tsu(PLL)).
Set the CM11 bit to “1” (PLL clock for the CPU clock source).
END
NOTES :
1. PLL operation mode can be entered from high speed mode.
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