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M16C/62P Group (M16C/62P, M16C/62PT)
6. Voltage Detection Circuit
Rev.2.41
Jan 10, 2006
Page 50 of 390
REJ09B0185-0241
Figure 6.5
Low Voltage detection Interrupt Generation Block
Figure 6.6
Low Voltage Detection Interrupt Generation Circuit Operation Example
Low Voltage detection interrupt generation circuit
Watchdog
timer interrupt
signal
VC27
VC13
Low Voltage detection Circuit
D4INT clock (the
clock with which it
operates also in
wait mode)
D42
DF1, DF0
1/2
00b
01b
10b
11b
1/2
1/2
1/8
Non-maskable
interrupt signal
Oscillation stop,
re-oscillation
detection
interrupt signal
Low Voltage
detection
interrupt
signal
Watchdog Timer Block
This bit is set to “0” (not detected) by program.
Watchdog timer
underflow signal
D43
D41
CM02
WAIT instruction (wait mode)
D40
VCC1
VREF
+
-
Noise
Rejection
(Rejection Range : 200 ns)
Low Voltage
detection signal
The Low Voltage detection signal
becomes “H” when the VC27 bit is
set to “0” (disabled)
Noise Rejection
Circuit
Digital
Filter
CM10
The D42 bit is set to “0” (not detected)
by program. The VC27 bit is set to “0”
(voltage down detect circuit disabled),
the D42 bit is set to “0”.
Output of the digital filter
(2)
D42 bit in D4INT register
NOTES :
1. D40 bit in the D4INT register is set to “1” (low voltage
detection interrupt enabled).
2. Output of the digital filter is shown in Figure 6.5.
Low Voltage
detection
interrupt signal
No low voltage detection interrupt signals are
generated when the D42 bit is “H”.
sampling
VC13 bit in VCR1 register
VCC1
sampling
sampling
sampling
Set to “0” by program (not detected)
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