M16C/62P Group (M16C/62P, M16C/62PT)
Appendix 2. Difference between M16C/62P and M16C/30P
Rev.2.41
Jan 10, 2006
Page 388 of 390
REJ09B0185-0241
NOTES:
1. About the details and the electric characteristics, refer to hardware manual.
Appendix Table 2.2 Function Difference (1)
(1)
Item
M16C/62P
M16C/62A
Timers A, B count
source
Selectable: f1, f2, f8, f32, fC32
Selectable: f1, f8, f32, fC32
Timer A two-phase
pulse signal
processing
Function Z-phase (counter reset) input
No function Z-phase (counter reset) input
Timer functions for
three-phase motor
control
Function protect by protect register
Count source is selected:
f1, f2, f8, f32, fC32
Dead time timer count source is selected:
f1, f1 divided by 2, f2, f2 divided by 2
Three-phase output forcible shutoff function
based on NMI input is available, output
polarity change, carrier wave phase
detection.
Function protect by protect register
Count source is selected:
f1, f8, f32, fC32
Dead time timer count source is fixed at f1
divided by 2
Serial I/O
(UART0 to UART2)
(UART, clock synchronous, I
2
C bus, IEBus)
x 3
(UART, clock synchronous) x 2
(UART, clock synchronous, I
2
C bus, IEBus)
x 1
UART0 to UART2,
SI/O3, SI/O4 count
source
Select from f1SIO, f2SIO, f8SIO, f32SIO
Select from f1, f8, f32
Serial I/O RTS timing
Assert low when receive buffer is read
Assert low when reception is completed
UART0 to UART2
Overrun Error
Generation Timing
This error occurs if the serial I/O started
receiving the next data before reading the
UiRB register (i=0 to 2) and received the 7
th bit of the next data (clock synchronous)
This error occurs if the serial I/O started
receiving the next data before reading the
UiRB register and received the bit one
before the last stop bit of the next data
(UART)
This error occurs when the next data is
ready before contents of UARTi receive
buffer register are read out
CTS/RTS separate
function
Have
None
UART2 data transmit
timing
After data was written, transfer starts at the
2nd BRG overflow timing
(same as UART0 and UART1)
After data was written, transfer starts at the
1st BRG overflow timing
(Output starts one cycle of BRG overflow
earlier than UART0 and UART1)
Serial I/O sleep
function
None
Have
Serial I/O I
2
C mode
Start condition, stop condition:
Auto-generationable
Start condition, stop condition:
Not auto-generationable
Serial I/O I
2
C mode
SDA delay
Only digital delay is selected as SDA delay
SDA digital delay count source: BRG
Analog or digital delay is selected as SDA
delay
SDA digital delay count source: 1/ f(XIN)
SI/O3, SI/O4 clock
polarity
Selectable
Fixed
A/D Converter
10 bits X 8 channels
Expandable up to 26 channels
10 bits X 8 channels
Expandable up to 10 channels
A/D converter
operation clock
Selectable: fAD, fAD divided by 2, 3, 4,
6, 12
Selectable: fAD, fAD/2, fAD/4
A/D Converter Input Pin
Select from ports P0, P2, P10
Fixed at port P10
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