M16C/62P Group (M16C/62P, M16C/62PT)
14. DMAC
Rev.2.41
Jan 10, 2006
Page 127 of 390
REJ09B0185-0241
NOTES:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the interrupt
control register.
2. The selectable factors of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 0020h to 003Fh) are accessed by the DMAC.
Table 14.1
DMAC Specifications
Item
Specification
No. of Channels
2 (cycle steal method)
Transfer Memory Space
• From any address in the 1-Mbyte space to a fixed address
• From a fixed address to any address in the 1-Mbyte space
• From a fixed address to a fixed address
Maximum No. of Bytes Transferred
128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
DMA Request Factors
(1, 2)
Falling edge of INT0 or INT1
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrupt requests
A/D conversion interrupt requests
Software triggers
Channel Priority
DMA0 > DMA1 (DMA0 takes precedence)
Transfer Unit
8 bits or 16 bits
Transfer Address Direction
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer Mode
Single Transfer
Transfer is completed when the DMAi transfer counter (i = 0 to 1)
underflows after reaching the terminal count.
Repeat Transfer
When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is
continued with it.
DMA Interrupt Request Generation Timing
When the DMAi transfer counter underflowed
DMA Start up
Data transfer is initiated each time a DMA request is generated when the
DMAE bit in the DMAiCON register = 1 (enabled).
DMA Shutdown
Single Transfer
• When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
Repeat Transfer
When the DMAE bit is set to “0” (disabled)
Reload Timing for Forward Address Pointer
and Transfer Counter
When a data transfer is started after setting the DMAE bit to “1”
(enabled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
DMA Transfer Cycles
Minimum 3 cycles between SFR and internal RAM
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