M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
Rev.2.41
Jan 10, 2006
Page 183 of 390
REJ09B0185-0241
Figure 17.7
UiMR Register
UARTi Transmit/Receive Mode Register (i=0 to 2)
Address
After Reset
03A0h, 03A8h, 0378h
00h
Bit Symbol
Function
RW
NOTES :
1.
2.
3.
Internal/External Clock Select
Bit
0 : Internal clock
1 : External clock
(1)
Symbol
SMD1
Bit Name
U0MR to U2MR
IOPOL
RW
RW
RW
CKDIR
PRYE
RW
RW
Stop Bit Length Select Bit
0 : 1 stop bit
1 : 2 stop bits
STPS
b7 b6 b5 b4 b3 b2 b1 b0
SMD2
RW
SMD0
RW
Serial I/O Mode Select Bit
(2)
b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I
2
C mode
(3)
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set except above
RW
To receive data, set the corresponding port direction bit for each RXDi pin to “0” (input mode).
Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).
Odd/Even Parity Select Bit
Effective w hen PRYE = 1
0 : Odd parity
1 : Even parity
PRY
Parity Enable Bit
TXD, RXD I/O Polarity Reverse
Bit
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
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