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VXIbus Interface 

5.  Set register 8130 with the value corresponding to bits 21-16 of the VMEbus 

address with the two low order bits of the register set to 0. 

 

VMEbus Address bits 21-16 

Res 

Res 

6.  Map the address.  

7.  Write the data 

 

 

Microsoft C code for Example 2 - 

 

LWORD addr;   /* 32-bit A32 address */ 

BYTE  data; 

BYTE  far * wptr; 

 

 

outp(0x8102,(inp(0x8102)|2));  

 

 /* set VME access bit */ 

outp(0x8150,(WORD)(addr >> 24));          /* A31-A24 */ 

outp(0x8151,2 | (((addr << 8) >> 30) << 6)); 

  /* A23-A22 and address modifier for A32 supervisory data access */ 

outp(0x8130,(WORD)((addr << 10) >> 24);  /* A21-A16 */ 

wptr = (BYTE far *) (0xE00 (addr & 0X0000FFFFL)); 

*wptr = data;                            /* Write through window */ 

The success of the access can be checked either by enabling BERR as an interrupt or 
by looking at the BERR bit in the event state register (8154) after each access.  Since 
writes are pipelined, software that looks at the BERR bit should first wait until the 
DONE bit is set. 

7

7

VXIbus Interrupt Handler 

Although software available for the EPC-7 shields the user from the details of 
interrupt handling, the following information is provided for the reader who needs 
further detail. 

The relationship between VME/VXI interrupts (and other interrupt-causing events) 
and an interrupt as seen by a program is shown in the following diagram. 

Page 71 

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Summary of Contents for EPC-7

Page 1: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

Page 2: ... Koll Parkway Beaverton OR 97006 Phone 503 646 1800 FAX 503 646 1850 ______________________________________________________________________ 07 0103 02 September 1994 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...rademarks of International Business Machines Corporation 386 and 486 are trademarks of Intel Corporation Microsoft and MS DOS are registered trademarks of Microsoft Corporation February 1992 Copyright 1992 1994 by RadiSys Corporation All rights reserved Page ii Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 4: ...if the product is damaged during installation of the modifications this warranty does not cover repair or replacement This warranty in no way warrants suitability of the product for any specific application IN NO EVENT WILL RADISYS BE LIABLE FOR ANY DAMAGES INCLUDING LOST PROFITS LOST SAVINGS OR OTHER INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT EVEN I...

Page 5: ...EPC 7 Hardware Reference NOTES Page iv Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 6: ...necting Peripherals to the EPC 7 12 Monitor 12 Keyboard 12 Serial Port 13 Parallel Printer Port 13 SCSI Port 13 External Clock Input 14 External Clock Output 14 External Trigger 14 4 Configuring the BIOS Setup 15 Power On Screen Display 15 BIOS Setup Screen 16 EXM Configuration 18 Fixed Disk Menu 20 User Definable Drive Types 22 Disk Formatting 23 Low level IDE AT Disk Formatting 23 Page v Artisan...

Page 7: ...oppy Connector 42 7 VXIbus Interface 43 Concepts 43 Memory Map 43 Direct VMEbus Accesses 44 Byte Ordering 45 Slave Accesses from the VMEbus 48 Self Accesses Across the VMEbus 48 Read Modify Write Operations 49 VMEbus Interrupt Response 50 Registers Specific to EPC 7 50 Register State after Reset 66 VXIbus Mapped Registers 67 Supported Address Modifiers 68 Low Level Programming the VMEbus Interface...

Page 8: ...ooting 81 Common Error Messages 84 SCSI related problems 89 10 Support and Service 91 Appendix A Interrupts and DMA Channels A 1 Appendix B I O Map B 1 Appendix C Using the EPC 7 AM C 1 Index I 1 Page vii Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 9: ... of SIMM Sockets 79 Tables Table 1 EPC 7 Environmental Specs With No Internal Disk Drives 2 Table 2 EPC 7 Environmental Specs With Floppy and Hard Drives 3 Table 3 Additional EPC 7 Specifications 4 Table 4 Fixed Disk Configuration Example 23 Table 5 Physical Address Space Mapping 26 Table 6 DB 9 Pinout 35 Table 7 COM2 10 Pin Header Pinout 35 Table 8 DB 25 LPT1 Pinout 36 Table 9 Keyboard Connector ...

Page 10: ...drive and sample the TTL and ECL trigger lines The EPC 7 is compatible with the IBM PC architecture and contains standard front panel connectors for PC serial and parallel ports The keyboard port is PS 2 style In addition the front panel contains a SCSI 2 port and cable connectors for external clock and trigger signals Depending on the model the EPC 7 contains three or four front panel expansion s...

Page 11: ...sion gradient Cooling For 10 C rise airflow of 2 liters per second against 0 014mm H2O backpressure Humidity operating 5 95 noncondensing storage 5 95 noncondensing Altitude operating 0 10 000 ft 3000 m storage 0 40 000 ft 12 000 m Vibration operating 0 015 inch 0 38 mm P P displacement with 2 5 g peak max acceleration over 5 2000 Hz storage 0 030 inch 0 76 mm P P displacement with 5 0 g peak max ...

Page 12: ...0 80 noncondensing 26 C max wet bulb storage 5 95 noncondensing 48 C max wet bulb Altitude operating 0 10 000 ft 3000 m storage 0 40 000 ft 12 000 m Vibration operating 0 015 inch 0 38 mm P P displacement with 0 6 g peak max acceleration over 5 500 Hz storage 0 030 inch 0 76 mm P P displacement with 2 0 g peak max acceleration over 5 500 Hz Shock operating 5 g 11 ms duration half sine shock pulse ...

Page 13: ... Weight without EXMs 5 5 lb 2 6 kg VME master address A16 A24 A32 master transfer D08 EO D16 D32 RMW slave address A16 A24 A32 slave transfer D08 EO D16 D32 RMW interrupter I 1 7 interrupt handler D08 O D16 IH 1 7 requester ROR RONR arbiter RRS PRI system controller SYSCLK IACK daisy chain bus timer VXI device type message based protocols cmdr master interrupter manufacturer code 4076 RadiSys Corp...

Page 14: ...controller and the VMEbus system controller Every VXIbus system needs a module that performs the VMEbus system controller functions generation of the 16 MHz SYSCLK signal arbitration of the bus detection of bus timeout conditions and initiation of the interrupt acknowledge daisy chain and the VXIbus slot 0 functions generation of the 10 MHz ECL CLK10 signals and control of the MODID module identif...

Page 15: ...iguration differing widely from the actual configuration Power on selftest reports a VXI failure CLK10 and CLK10 signals are not being driven or are out of spec on the backplane The system resource manager could not detect the presence of a non slot 0 EPC 7 Power on selftest reports NO SYSCLK System hangs typically while running the resource manager If any of these conditions occur check the confi...

Page 16: ...i e empty slots and slots occupied by some multi slot instruments need to be jumpered to allow the signals to pass through to other instruments in the system x x x O U T x x x I N x x x O U T x x x I N x x x O U T x x x I N V X I b u s S l ot s x x x I N x x x O U T Figure 2 Daisy Chain Signal Concept The Slot 0 controller board initiates each daisy chain signal Each VXIbus slot to the right of th...

Page 17: ...e not or if the VXIbus slot is empty all or some of these signals must be jumpered See Figure 3 below indicates jumper needed SingleBoardComputer that onlyhandles IACK BG3 Dumb Slave Doesnot handle anyof thesignals BG0 BG1 BG2 BG3 IACK Figure 3 VXIbus Backplane Jumper Examples Page 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 18: ...acturers handle jumpers and DIP switches in different ways some provide stake pins on the rear of the backplane while others provide stake pins or DIP switches on the front of the backplane These stake pins can be located in several different places If the stake pins are on the rear of the backplane the most common place is in the middle of the J1 connector as shown in Figure 5 below This can be j...

Page 19: ...lot 6 between Slots 5 and 6 Consult your VXI chassis reference manual or contact the chassis manufacturer if you are unsure where to jumper your particular system The EPC 7 occupies two VXI slots and correctly handles all bus grant and IACK signals for both slots No jumpers are needed for these two slots If an EPC 7AM or EPC 7MC is also being used it occupies a third VXI slot Jumpers must be insta...

Page 20: ...Before Installation NOTES 2 2 Page 11 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 21: ...s insertion to the right of certain other types of modules These keys prevent problems associated with incompatible signal levels on the VXI daisy chained Local Bus Although the EPC 7 does not use the Local Bus its ability to be a slot 0 controller means that it uses what would otherwise be leftside Local Bus lines for TTL MODID lines Therefore the key prevents the EPC 7 from being installed to th...

Page 22: ...ntroller for connection to an analog VGA monitor Use of the EXM 13A is summarized below Consult the EXM 13A reference manual for further details Monitors that can be used with the EXM 13A are VGA compatible monitors i e those compatible with the IBM PS 2 and with PC VGA add in cards and multiscan multifrequency or multisync monitors Refer to the EXM 13A manual for more information If you cannot ma...

Page 23: ...nnector when the connector is not being used will reduce the possibility of ESD electrostatic discharge damage through the connector Parallel Printer Port The parallel port on the front panel is compatible with the corresponding DB 25 LPT1 connector on IBM PCs and compatibles Typically it is used to connect printers and software security keys SCSI Port The SCSI connector is a high density 50 pin s...

Page 24: ...ce for more information External Clock Output A second SMB connector provides a TTL form of the CLK10 clock It can drive a 50 ohm line This is typically used to synchronize multiple VXI mainframes External Trigger A third SMB connector provides for an external TTL trigger signal input or output When configured as an input it is not resistively terminated and presents one FAST TTL unit load IIH 0 0...

Page 25: ...orporation BIOS V3 05 TESTING INTERRUPT CONTROLLER 1 OK TESTING INTERRUPT CONTROLLER 2 OK TESTING CMOS BATTERY OK TESTING CMOS CHECKSUM OK TESTING VME INTERFACE OK TESTING VXI INTERFACE OK SIZING SYSTEM MEMORY 640K FOUND TESTING SYSTEM MEMORY 640K OK CHECKING UNEXPECTED INTERRUPTS AND STUCK NMI OK TESTING PROTECTED MODE OK SIZING EXPANSION MEMORY 7168K FOUND TESTING MEMORY IN PROTECTED MODE 7808K ...

Page 26: ...el such as Microsoft Windows cause this key sequence to be interpreted differently or not at all It should always work however when the DOS operating system prompt is shown on the screen The setup function can be invoked prior to system booting by pressing CTRL ALT ESC immediately after the initial selftest screen is cleared The main setup screen will be similar to the following RadiSys EPC 7 CMOS...

Page 27: ...if a configuration error is found The selections are 1 halt on all errors 2 ignore all errors 3 ignore keyboard errors allows operation without a keyboard 4 ignore disk errors and 5 ignore keyboard and disk errors DISKETTE DRIVE This field identifies the type of floppy disk drive installed as the A drive If the EPC 7 has a floppy drive installed the proper setting is for a 3 5 1 44 MB floppy disk ...

Page 28: ...and disabled states The enabled state enables the controllers for these I O ports The disabled state means that the associated I O port is disabled and the I O addresses and IRQs associated with the controller for the port are not responded to by the controller Putting a port in the disabled state allows use of I O modules that may have conflicting addresses or IRQs with the built in ports EXM Con...

Page 29: ...s the EXM slot in which the EXM is installed See the figure below to determine which slot each EXM occupies Note that when installed the floppy disk drive occupies EXM slot 0 Dotted lines indicate EXM slot numbers for an optional EPC 7MC module carrier C P U 0 1 2 4 3 5 Figure 9 EXM Slot Numbering ID is a hard wired ID value Each type of EXM has a unique ID value OB1 OB2 are two option bytes of co...

Page 30: ... used COM2 is available on the EPC 7AM adapter module Refer to Appendix C for installation information concerning the EPC7 AM 2 Use DMA channels 1 3 6 and 7 Channels 0 and 5 may also be used depending on whether you are using the SCSI interface and how it is configured 3 Do not select I O addresses that conflict with those in the EPC 7 A complete list appears in Appendix B For instance I O address...

Page 31: ...ive use the user definable drive types 48 or 49 None Choose None if there is no hard disk present SCSI Choose SCSI to activate the built in SCSI BIOS Use this option only if you are not using a loadable device driver such as those included with the EZ SCSI software There are no fixed disk characteristics to select because the BIOS determines them dynamically If Drive C is set to SCSI Drive D must ...

Page 32: ... Sectors is 1 MBytes is a display only field calculated by the BIOS Move the cursor to each field Cyls Heads and Sectors and type the value for that field If a drive label exists on the right side panel refer to Figure 11 use the parameters listed on the label When installing a user supplied replacement IDE hard disk consult the hard disk manual for the correct values to use for cylinders heads an...

Page 33: ...on Example After the Fixed disk s have been configured press F10 to save the data or ESC to ignore the changes In either case you will be returned to the main setup screen Disk Formatting The hard disk in the EPC 7 is an IDE disk which is hard sectored therefore it does not require low level formatting Depending on the context in which you ordered the EPC 7 the disk is either bootable containing a...

Page 34: ...stems Inc QAPlus from DiagSoft Inc AMIDIAG from American Megatrends Inc or SuperSoft Service Diagnostics from SuperSoft Inc Low level formatting is rarely necessary and in fact is not possible on some of the new higher capacity IDE drives 4 4 Page 24 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 35: ...diSys data path switch gate array pair VXIbus VXI gate arrays and control logic BIOS Serial and parallel port controller 8242 controller ATU ASIC Reset switch Battery Speaker DMA interrupt ctrl clock timers control reset logic DRAM SCSI controller Floppy disk controller IDE disk interface 32 16 64 EXM 16 32 8 16 8 Expansion Interface keyboard VXI bus 5 5 Figure 12 Data Path Block Diagram Page 25 A...

Page 36: ...by bit in register 8102h 000F0000 000FFFFF DRAM used for BIOS shadowing Write protected 00100000 00FDFFFF DRAM or EXM expansion interface to DRAM to the extent of the value of MEMS in the memory mode register 00FE0000 00FFFFFF Mapped to BIOS ROM or DRAM see bit MDFF in memory mode register 01000000 03FFFFFF DRAM or EXM expansion interface see bit MEMS in the memory mode register 04000000 0FFFFFFF ...

Page 37: ...y memory areas defined by the PC architecture as well as memory mapped to the VXIbus and potentially some mapped to the EXM expansion interface cannot be safely cached What is cached is the first 640 KB of memory and all DRAM above 1 MB meaning the following address ranges 0000 0000 to 0009 FFFF 0010 0000 to 03FF FFFF The use of a cache with dual port memory i e DRAM in the EPC 7 that is also acce...

Page 38: ...I software does not ship with the EPC 7 but a separate SCSI software and manual package is available at not charge Contact RadiSys Technical Support for ordering information If you need to use SCSI software with a non DOS Windows operating system contact Adaptec sales at 1 800 442 7274 The controller is compatible with SCSI 2 and CCS common command set It supplies a transfer rate of up to 5 MB s f...

Page 39: ...d TOD clock when system power is not present At 60 C the battery should have a shelf life of over four years In a system that is powered on much of the time and where the ambient power off temperature is significantly lower than 60 C the battery is estimated to have a life of 10 years 5 5 Floppy Hard Disk P2 P1 SIMMs Battery EPC 7 Front Figure 13 EPC 7 Battery Location The battery holder is for a ...

Page 40: ...e spring until it snaps into the holder Ensure that the spring has not been damaged and that it is in firm contact with and applying downward pressure on the battery cell Watchdog Timer The EPC 7 contains a continually running timer having a period of either about 0 2 or 6 7 seconds software selectable This event may be enabled as a source of the IRQ10 interrupt or as a hardware reset depending on...

Page 41: ...he means to assert the EXMID signal Further information on the EXM expansion interface its connectors and standards for building EXMs is available upon request VXIbus Interface 5 5 The EPC 7 module connects to the VXIbus J1 and J2 connectors in the left of the two slots occupied by the EPC 7 and to the J1 connector in the right slot On the left P1 connector the EPC 7 uses all of the defined VME VX...

Page 42: ...secs When the EPC 7 is configured as the slot 0 controller this timeout cannot be disabled and the duration cannot be changed Although the EPC 7 provides the required timeout function for data transfer time out it does not provide the optional bus grant timeout If another master has been granted permission to use the data bus but does not access or relinquish the data bus the bus will be hung inde...

Page 43: ...ertion of the VXI SYSRESET signal when bit SRIE in the status control register is zero also places the EPC 7 in the soft reset state except the PASS and RDY bits are not cleared in this case Four conditions cause a full hardware reset of the EPC 7 5 5 SYSRESET signal when enabled in the status control register Front panel reset switch Expiration of the watchdog timer when bit WDTR in the module st...

Page 44: ...nnector Internal IDE disk connector Disk power Front P1 Connector to cable to secondary P1 connector for power Configuration jumpers Figure 15 PCB Layout Connectors to EXM expansion interface subplane DRAM SIMM sockets P2 Speaker header COM2 header Page 34 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 45: ...t addressable as PC serial port COM2 exists in the form of a 10 pin header on the printed circuit board near the bottom of the front panel Pin 1 is the pin closest to the front panel and the bottom of the EPC 7 printed circuit board The header is defined in the table below Pin Signal Pin Signal 1 Carrier detect 6 Clear to send 2 Data set ready 7 Data terminal ready 3 Receive data 8 Ring indicator ...

Page 46: ...ignal ground 10 Acknowledge 23 Signal ground 11 Busy 24 Signal ground 12 Paper end 25 Signal ground 13 Select Table 8 DB 25 LPT1 Pin out The keyboard connector is an IBM PS 2 style connector It is not compatible with the older larger 5 pin keyboard connectors but an adapter cable is provided The connector pins are defined in the table below Pin Signal Pin Signal 1 Data 4 5V 2 unconnected 5 Clock 3...

Page 47: ... DB 1 3 Ground 28 DB 2 4 Ground 29 DB 3 5 Ground 30 DB 4 6 Ground 31 DB 5 7 Ground 32 DB 6 8 Ground 33 DB 7 9 Ground 34 DB P 10 Ground 35 Ground 11 Ground 36 Ground 12 Ground 37 Ground 13 unconnected 38 TERMPWR 14 Ground 39 Ground 15 Ground 40 Ground 16 Ground 41 ATN 17 Ground 42 Ground 18 Ground 43 BSY 19 Ground 44 ACK 20 Ground 45 RST 21 Ground 46 MSG 22 Ground 47 SEL 23 Ground 48 C D 24 Ground ...

Page 48: ...e front panel TRIG connector is a miniature SMB coax connector Whether it is an input or output is determined by the external trigger register refer to Chapter 7 VXIbus Interface The input signal must be a TTL signal capable of driving a 74F04 input see CLK IN As an output TRIG can drive a 50 ohm line to 2 25V VXI Signal Usage The following table shows the usage of the VXI expansion interface sign...

Page 49: ...CLK A17 IO 22 IACKOUT O SERDAT A16 IO 23 AM4 IO GND G A15 IO 24 A07 IO IRQ7 IO A14 IO 25 A06 IO IRQ6 IO A13 IO 26 A05 IO IRQ5 IO A12 IO 27 A04 IO IRQ4 IO A11 IO 28 A03 IO IRQ3 IO A10 IO 29 A02 IO IRQ2 IO A09 IO 30 A01 IO IRQ1 IO A08 IO 31 12V P 5VSTDBY 12V P 32 5V P 5V P 5V P 6 6 Table 12 VXIbus Signal Usage Notes to preceding table 1 SYSCLK as an input is used only in conjunction with the SYSC bi...

Page 50: ...LBUSC05 13 5 2V P 5V P 2V P 14 MODID06 IO D16 IO LBUSC06 15 MODID05 IO D17 IO LBUSC07 16 GND G D18 IO GND G 17 MODID04 IO D19 IO LBUSC08 18 MODID03 IO D20 IO LBUSC09 19 5 2V P D21 IO 5 2V P 20 MODID02 IO D22 IO LBUSC10 21 MODID01 IO D23 IO LBUSC11 22 GND G GND G GND G 23 TTLTRG0 IO D24 IO TTLTRG1 IO 24 TTLTRG2 IO D25 IO TTLTRG3 IO 25 5V P D26 IO GND G 26 TTLTRG4 IO D27 IO TTLTRG5 IO 27 TTLTRG6 IO ...

Page 51: ...06 BG1OUT O D14 8 D07 BG2IN I D15 9 GND G BG2OUT O GND 10 SYSCLK BG3IN I SYSFAIL 11 GND G BG3OUT O BERR 12 DS1 BR0 SYSRESET 13 DS0 BR1 LWORD 14 WRITE BR2 AM5 15 GND G BR3 A23 16 DTACK AM0 A22 17 GND G AM1 A21 18 AS AM2 A20 19 GND AM3 A19 20 IACK GND A18 21 IACKIN I SERCLK A17 22 IACKOUT O SERDAT A16 23 AM4 GND A15 24 A07 IRQ7 A14 25 A06 IRQ6 A13 26 A05 IRQ5 A12 27 A04 IRQ4 A11 28 A03 IRQ3 A10 29 A...

Page 52: ... 11 n c 12 DIR 13 GND 14 GND 13 n c 14 STEP 15 GND 16 MO 15 GND 16 WDATA 17 GND 18 DIR 17 GND 18 WGATE 19 GND 20 STEP 19 GND 20 TRK00 21 GND 22 WDATA 21 GND 22 WRPRT 23 GND 24 WGATE 23 GND 24 RDATA 25 GND 26 TRK00 25 GND 26 SIDE 27 GND 28 WRPRT 29 GND 30 RDATA 31 GND 32 SIDE 33 GND 34 DSKCH Table 15 34 pin and 26 pin Floppy Connector Pin outs Note Pins 7 9 and 11 on the 34 pin connector or pins 1 ...

Page 53: ... the 0E0000 0EFFFF E page window or by direct mapping above 256 MB The following summarizes the source of the VMEbus address lines for accesses through the E page A32 7 7 31 2423 2221 15 16 0 From port 8150 From port 8151 From port 8130 From 486 address bits 15 0 A24 23 2221 15 16 0 From From port 8151 port 8130 From 486 address bits 15 0 A16 15 0 From 486 address bits 15 0 It should be noted that...

Page 54: ...nibble is used to define the access mode and byte ordering For A32 space the high order 2 bits define the access mode leaving 30 bits available for addressing Thus only the first 1 Gigabyte of VMEbus A32 space is directly addressable All A24 and A16 space is directly addressable The chart following shows how this direct mapping is used 7 7 Address Range Access Mode Byte Order 1xxx0000 1xxxFFFF VME...

Page 55: ...he direct access mappings do not cover the entire VMEbus A32 address range and do not provide all VMEbus defined address modifier encodings but one can use the E page mechanism if needed to provide these Byte Ordering There are two fundamentally different ways of storing numerical values in byte loca tions in memory 7 7 Little endian characteristic of Intel microprocessors where the least signific...

Page 56: ...selected bytes pass straight through unchanged Little endian should only be used when reading or writing data between two Intel processor systems The results of using little endian byte ordering to transfer a double word integer between an Intel processor and a Motorola processor are shown below 486 Address M o t o r o l a Address Addr Addr 1 Addr 2 Addr 3 Addr Addr 1 Addr 2 Addr 3 LSB MSB 10 32 5...

Page 57: ... used Some compilers produce two 16 bit accesses when a 32 bit access is desired When this occurs again the data will be scrambled 7 7 When transferring a 32 bit floating point number special care must be taken to assure that both processors use the same floating point format that both systems expect the mantissa and exponent in the same byte locations As long as this is correct transferring a flo...

Page 58: ...r note the following 1 Any access that maps to local addresses 000A0000 000BFFFF 000D0000 000EFFFF to addresses mapped to the EPC 7 s EXM expansion interface and to addresses beyond the extent of the installed DRAM cause the EPC 7 to respond with BERR bus error 7 7 2 Write accesses to write protected DRAM terminate normally DTACK response but with no effect on the DRAM Enabling the EPC 7 as a slav...

Page 59: ...he LOCK instruction prefix with certain instructions All of these instructions perform a read followed by a write When such a read occurs that is mapped to the VMEbus the EPC 7 treats it as the start of a VME RMW cycle The next VME access from the CPU is treated as the write that terminates the RMW cycle Keep in mind that accesses that cross a 32 bit boundary are actually performed as two accesses...

Page 60: ...lue is the contents of register 815C For D16 and D32 interrupt acknowledge cycles the status ID value consists of 16 bits The upper eight bits are the upper half of the response register the value in I O port 814B and the lower eight bits are the contents of register 815C Registers Specific to EPC 7 Registers in the I O space that are specific to the EPC 7 are defined below Bit 7 Bit 6 Bit 5 Bit 4...

Page 61: ...ge High Reg lower 814C Message High Reg upper 814D Message Low Reg lower 814E Message Low Reg upper 814F VME A31 24 Address Reg 8150 VME Modifier Register VME WA23 22 BORD IACK AM5 AM4 AM2 AM1 8151 VME Interrupt State Reg IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR 8152 VME Interrupt Enable Reg IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR 8153 VME Event State Register 1 1 VXRCP SIGR WDT ACFA BERR SYSF 8154...

Page 62: ...ter TTL7 TTL6 TTL5 TTL4 TTL3 TTL2 TTL1 TTL0 8161 Clock Control Register 1 1 1 1 1 1 1 ENXC 8162 External Trigger Register 1 1 1 1 OUT Trigger line 8163 Trig Interrupt Enable Reg TTI7 TTI6 TTI5 TTI4 TTI3 TTI2 TTI1 TTI0 8164 7 7 The following additional registers do not reside in the I O space but are mapped into the VXI A16 address space 15 0 A24 Shared Mem Ptr High xx10 15 0 A24 Shared Mem Ptr Low...

Page 63: ...e for the VMEbus 11 means 3 10 means 2 01 means 1 00 means 0 RELM Bus release mode If set the bus release mode is ROR release on request otherwise it is the VXI RONR fair requester mode request on no request ARBM Arbitration mode This bit is pertinent only if the EPC 7 is jumpered to be the VXIbus slot 0 controller If set the EPC 7 is a priority arbiter other wise it is a round robin arbiter 7 7 S...

Page 64: ...gions are mapped to the EXMbus and reads come from DRAM When 0 writes are mapped to DRAM and reads from 000Cxxxx are mapped to the EXMbus and reads from 000Fxxxx are mapped to DRAM This bit is used by the BIOS to copy itself and video and SCSI BIOS s into DRAM MEMS These bits control the address decoding i e which addresses map to DRAM versus the EXMbus They are set by the BIOS with the following ...

Page 65: ...ds to a 4 MB range in the A24 space and bit A32 in the ID register is 0 S This read only bit specifies if the EPC 7 has been jumpered as a slot 0 controller 1 denotes no and 0 denotes yes S forms part of the VXI model code which is 239 S 0 denoting slot 0 controller or 495 S 1 Status Control Reg lower SRIE 1 SYSC 1 RDY PASS NOSF RSTP 8144 Status Control Reg upper SLE MODI SYSR 1 1 1 1 1 8145 This ...

Page 66: ...EPC 7 front panel is lit The VXI SYSFAIL line is asserted whenever PASS 0 and NOSF 0 This bit is read only when accessing this register from the VXI A16 space Setting the RSTP bit always clears this bit NOSF SYSFAIL inhibit If set the EPC 7 cannot assert the VXI SYSFAIL line RSTP Reset EPC Setting this bit will reset portions of the VME VXI interface of the EPC 7 Reset behavior is discussed in the...

Page 67: ...e handling and several EPC 7 dependent bits DOR RAM bit available to software for VXI communication protocols DIR RAM bit available to software for VXI communication protocols ERR RAM bit available to software for VXI communication protocols RRDY Read ready A 1 denotes that the message registers contain outgoing data to be read by another device RRDY is cleared when the message low register is rea...

Page 68: ... clears RRDY A write into all or the lower 8 bits of the message low register clears WRDY A read or write to all or the lower 8 bits of the message high register clears ABMH A read of the alternate response register clears MLCK if WRDY is set Message High Reg lower 814C Message High Reg upper 814D 7 7 Message Low Reg lower 814E Message Low Reg upper 814F The message registers may be used to implem...

Page 69: ...o define the VXIbus access as an interrupt ac knowledge cycle The interrupt being acknowledged must be encoded by software as a value on address lines A1 A3 VME Interrupt State Reg IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR 8152 This read only register defines the state of the VXI and message interrupts IRQx If clear 0 the associated VXI interrupt line is asserted MSGR If clear 0 a message interrupt ...

Page 70: ...tate register A 1 denotes that the corresponding event is enabled as an interrupt If any bit in this register is a 1 and the corresponding bit in the event state register is a 0 the EPC 7 IRQ10 interrupt is asserted Software may then examine the interrupt and event state registers to determine the cause The following two bits are read only state bits DSOR Clear whenever either of the VXI DS0 DS1 d...

Page 71: ...on the VXI backplane The bits named MO00 MO12 are associated with signals MODID00 MODID12 When a write occurs to this register 8159 the EPC 7 drives the MODID signals on the backplane A read of this register 8159 terminates the driving of the signals the value returned from this driver terminating read is not specified and should not be used All other reads of both registers sample the MODID signa...

Page 72: ...apter 5 for more information SBER Sticky BERR This bit is cleared whenever a VXI data transfer bus access by the EPC 7 is terminated by a BERR By initially setting the bit and then performing a series of data transfers software can determine if a bus error occurred Alternatively software could examine the BERR bit in the event state register after each access or enable the BERR event to generate a...

Page 73: ... Bus timeout enable Enables the slot 0 bus timeout timer This is used by the BIOS WDTR Watchdog timer reset enable If 1 expiration of the watchdog timer generates a reset of the EPC 7 If 0 only the WDT event is signaled FWDT Fast watchdog timer If clear the period of the watchdog timer is about 6 7 seconds If set the period is about 210 ms A read of the module status control register also has a si...

Page 74: ...n internal 10 MHz clock having an accuracy of 100 ppm A write to this register will cause the CLOCK10 signal to stay in the high state for the duration of the I O write cycle to meet the requirements of rule B 6 4 of the VXI specification If ENXC is set and there is no external clock source connected it cannot be cleared by writing 0 to the register a hardware reset will be necessary This provides...

Page 75: ...determine the cause The following registers are mapped as offsets from the EPC 7 s VXI A16 base address 15 0 A24 Shared Mem Ptr High xx10 15 0 A24 Shared Mem Ptr Low xx12 15 0 A32 Shared Mem Ptr High xx14 15 0 A32 Shared Mem Ptr Low xx16 These registers form a 32 bit address register for the optional shared memory protocol There are only a total of 32 physical register bits If bit A32 in the ID re...

Page 76: ... condition is true For 16 bit messages the sender writes into the message low register For 32 bit messages the sender must write into the message high register before writing into the message low register Register State after Reset 7 7 A hardware reset of the EPC 7 not a keyboard CTRL ALT DEL reset clears all of the register bits to 0 in the following registers except those bits defined as a const...

Page 77: ...ars in the ULA register The mapping of registers in the A16 space is shown in the following table For registers that are also accessible from within the EPC 7 via an I O address the I O address is given in parentheses Offset Upper byte Lower byte 0 ID 8141 ID 8140 2 Device type 8143 Device type 8142 4 Status control 8145 Status control 8144 6 Slave offset 8147 Slave offset 8146 8 Protocol signal 8...

Page 78: ...ed that rather than performing accesses in this low level hardware de pendent form the BusManager component of the EPConnect software package be used instead VMEbus Accesses Two examples are given here including both a verbal description and the Microsoft C source code for performing VMEbus accesses through the E page Example 1 performs a 16 bit read from the VMEbus A16 space 1 Set the EVME access...

Page 79: ...ues are generated by hardware Bits 7 6 Since the A16 space does not use VMEbus address lines A23 A22 set these values to 1 VME WA 23 22 11 Bit 5 Set the byte order to little endian BORD 0 Bit 4 Clear the IACK bit so this is not an interrupt acknowledge cycle IACK 0 Bits 3 0 Use the address modifier in binary form to determine the appropriate values for these bits 2Dh 00101101b Bit 3 Address Modifi...

Page 80: ... upper 16 bits of the VME address need to be stored in the appropriate registers 1 Set the VME access bit in Register 8102 2 Set register 8150 with the value corresponding to the 8 high order address bits 7 7 VMEbus Address bits 31 24 WA31 24 3 Determine the correct address modifier for A32 supervisory access 4 Calculate the value and set register 8151 as follows VME WA23 22 BORD IACK AM5 AM4 AM2 ...

Page 81: ...ptr data Write through window The success of the access can be checked either by enabling BERR as an interrupt or by looking at the BERR bit in the event state register 8154 after each access Since writes are pipelined software that looks at the BERR bit should first wait until the DONE bit is set 7 7 VXIbus Interrupt Handler Although software available for the EPC 7 shields the user from the deta...

Page 82: ...ched meaning that a read of the state register shows the actual state of the signals at the instant of the read The exceptions are 1 BERR which is a sticky bit meaning that the bit signifies whether BERR had ever been asserted the VXR register bit and 2 the TTL trigger signals which for interrupt purposes are taken from the trigger latch register The convention used is that a 0 bit signifies an as...

Page 83: ...h to switch to another stack a must under DOS and may wish to save the state of the VME modifier and address registers if you will be using them 2 To prevent reentry to the interrupt handler mask off all the inter rupts events or mask off the IRQ10 interrupt Reenable what you have masked off at the end of the interrupt handler 3 Acknowledge the interrupt by sending end of interrupt to both 8259 in...

Page 84: ...les that are accessed by the 486 by implicit locked accesses are not mapped into VXI This would only be a concern for user written operating systems 7 7 VXIbus RMW read modify write cycles can be performed through use of the 486 s LOCK instruction prefix with certain instructions All of these instructions perform a read followed by a write When such a read occurs that is mapped to the VXIbus the E...

Page 85: ...8159 BWM 8151 and the ETR 8163 registers are cleared by the VXT bit Finally TTLTRIG0 drive is disabled while the VXR is asserted This bit is treated differently than the other Trigger drive bits since clearing the ETR may cause the external trigger to drive TTLTRIG0 Software can recognize the safe soft reset states in the following ways 7 7 1 Enable VXR interrupt When a VXR interrupt is handled ch...

Page 86: ...ne the source of the VXR Two conditions generate hardware resets that include resetting all of the hardware One is receipt of VME SYSREST with bit SRIE set The other is expiration of the watchdog timer period when bit WDA is set meaning that one wants the watchdog timer to generate a reset rather than an interrupt 7 7 Page 76 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURC...

Page 87: ...er single sided For 4 MB Use 4 each 256K x 36 SIMMs RadiSys P N 70 0032 We recommend Toshiba THM362500ASG 80 For 8 MB Use 2 each 1M x 36 SIMMs RadiSys P N 70 0042 8 8 We recommend Toshiba THM361000ASG 80 For 16 MB Use 4 each 1M x 36 SIMMs RadiSys P N 70 0042 We recommend Toshiba THM361000ASG 80 For 32 MB Not upgradeable This is a factory build time option only The 100 MHz EPC 7 memory configuratio...

Page 88: ...r 32 MB Use 2 each 4M x 36 SIMMs RadiSys P N 70 0075 For 64 MB Use 4 each 4M x 36 SIMMs RadiSys P N 70 0075 The EPC 7 SIMMs work in pairs When configuring an EPC 7 with two SIMMs the SIMMs should be placed in sockets 1 and 3 Sockets 2 and 4 should remain empty See Figure 18 below for SIMM socket locations 8 8 Page 78 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www art...

Page 89: ...p will display after the power on self test completes Press CTRL ALT ESC to enter the Main Setup Menu Verify that the top line of this screen shows the correct amount of memory Press F10 to save and F5 to confirm and reboot The system will reboot and no error messages should be displayed 8 8 Page 79 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 90: ...EPC 7 Hardware Reference NOTES 8 8 Page 80 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 91: ... and hard disk being accessed but provides no video Video adapter not fully seated Monitor or cable problem Video adapter failure EPC 7 cannot talk to EXM expansion interface Remove the video adapter Verify that the cable pins are not bent and the cable is fully seated in the video adapter If necessary try the monitor on another system to verify that the monitor is good Call RadiSys Technical Supp...

Page 92: ...V are good An EXM module is using the same interrupts as COM1 and or COM2 Verify that no other card in the EPC 7 subsystem is using IRQ3 or IRQ4 Call RadiSys Technical Support System hangs during boot process Master LED on RUN LED off Chassis has no Slot 0 controller providing bus timeout You are probably loading an expanded memory manager for example EMM386 EXE in your CONFIG SYS file This can ca...

Page 93: ...VXIbus Backplane Jumpers on page 7 Make sure that only 1 system is configured as the Slot 0 controller and that it is the left most system in the chassis Remove the EPC 7 and verify that no pins are bent Then reinsert the EPC 7 Power off then back on Verify that the results of the power on self test indicate VMEbus interface and VXIbus interface report ok 9 9 Page 83 Artisan Technology Group Quali...

Page 94: ... repeatedly the EPC 7 s battery has failed DISK BOOT FAILURE INSERT SYSTEM DISK AND PRESS ENTER Problem No boot disk could be found Solution s This could occur in several different ways Your hard disk may not have been partitioned into logical drive s PCs look for logical drives to boot from Hard disks are physical drives partitions are logical drives 9 9 Your BIOS setup screen has all disks disab...

Page 95: ...rive C cannot be initialized Solution s The EPC 7 uses an internal IDE interface and drive If it fails either the setting is wrong or the system needs repair If you are not using an IDE drive press CTRL ALT ESC to enter the BIOS setup program Press F3 to enter the Fixed disk menu Change the drive type to match the device being used EXM CONFIGURATION ERROR Problem The EXMs installed or not installe...

Page 96: ...roblem You are trying to access a logical drive e g A B that is not known to the operating system Solution s Select a different logical drive If you are trying to access a hard disk you may need to create the logical partition KEYBOARD ERROR OR NO KEYBOARD PRESENT Problem This message indicates that the system did not recognize a keyboard at power up or you pressed a key during the power on self t...

Page 97: ...STEM Problem Although the system could read the hard disk and find the active partition the operating system files could not be found Solution s This is can be caused by using a drive type number in the Fixed Disk Menu that does not match the type number used to format the hard disk Press CTRL ALT ESC to run the BIOS setup program Press F3 to enter the Fixed Disk Menu Select the correct drive type...

Page 98: ... drive and press any key NOT READY READING DRIVE Problem This is usually caused by not fully inserting a diskette into the floppy drive Solution s Eject the floppy diskette and reinsert making sure that the diskette seats completely into the floppy drive PARITY ERROR IN SEGMENT Problem This could be a software error reading a nonexistent memory area or a true hardware failure Solution s Attempt to...

Page 99: ...rive in the main setup menu must be set to specify NONE as the drive type The hard drive must be partitioned and formatted on the EPC 7 and the SCSI partition must be the active partition Run your operating system disk partitioning program like FDISK and set the primary partition active See your operating system manual for instructions on formatting a disk Always attempt to solve the problem yours...

Page 100: ...EPC 7 Hardware Reference NOTES 9 9 Page 90 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 101: ... next business day Technical Support Services are designed for customers who have purchased their products from RadiSys or a sales representative If your RadiSys product is part of a piece of OEM equipment or was integrated by someone else as part of a system support will be better provided by the OEM or system vendor that did the integration and understands the final product and environment Bulle...

Page 102: ...ol make it more convenient to receive their original products back after repair Warranty Repairs Products under warranty see warranty information in the front of this manual will have manufacturing defects repaired at no charge Products sent in for warranty repair that have no faults will be subject to a recertification charge Extended Warranties are available and can be purchased at a standard pr...

Page 103: ...able in a spares program There is a minimum billing charge associated with this program Arranging Service To schedule service for a product please call RadiSys Technical Support directly at 503 646 1800 Have the product model and serial numbers available along with a description of the problem A Technical Support representative will issue a Returned Materials Authorization RMA number a code number...

Page 104: ...g and a description of the suspected problem Any ancillary information that might be helpful with the debugging process will be appreciated Other Countries Contact the sales organization from which you purchased your RadiSys product for service and support 10 10 Page 94 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 105: ... NMI DRAM parity error EXM expansion interface I O channel check IRQ0 timer IRQ1 keyboard IRQ3 COM2 serial port IRQ4 COM1 serial port IRQ5 unassigned IRQ6 floppy disk controller IRQ7 LPT1 parallel port IRQ8 clock IRQ9 unassigned IRQ10 VXI interrupt event IRQ11 SCSI controller IRQ12 unassigned IRQ13 unassigned IRQ14 IDE disk IRQ15 unassigned Table 18 Interrupt Assignments Page A1 Artisan Technology...

Page 106: ...SCSI or unassigned see battery backed register 1 unassigned 2 floppy disk controller 3 unassigned 5 SCSI or unassigned see battery backed register 6 unassigned 7 unavailable Table 19 DMA Channels Page A2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 107: ...Set byte pointer R Clear byte pointer W 0D Temporary register R Master clear W 0E Clear mode reg counter R Clear all DMA req mask W 0F All DMA request mask 20 Interrupt controller 1 Port 0 21 Port 1 24 83000 Controller Data register 26 Index register 40 Timer Counter 0 41 Counter 1 42 Counter 2 43 Control W 60 Keyboard controller Data I O register 61 NMI status NMI status 64 Keyboard controller Co...

Page 108: ...96 EXM Configuration EXMID driver A0 Interrupt controller 2 Port 0 A1 Port 1 C0 DMA Channel 4 address C2 Channel 4 count C4 Channel 5 address C6 Channel 5 count C8 Channel 6 address CA Channel 6 count CC Channel 7 address CE Channel 7 count D0 Command status D2 DMA request D4 Command register R Single bit DMA req mask W D6 Mode D8 Set byte pointer R Clear byte pointer W DA Temporary register R Mas...

Page 109: ...Transfer control 0 register 342 Transfer control 1 register 343 Signal out register 344 Rate control register 345 Selection reselection ID register 346 Latched data register 347 Data bus register 348 Count 0 register 349 Count 1 register 34A Count 2 register 34B Interrupt status 0 register 34C Status 1 register 34D Status 2 register 34E Status 3 register 34F Status 4 register 350 Interrupt mode 0 ...

Page 110: ...ry control 8130 VME A21 16 address 8132 alias address of 8130 8134 alias address of 8130 8136 alias address of 8130 8140 VXI registers ID low 8141 ID high 8142 Device type low 8143 Device type high 8144 Status control low 8145 Status control high 8146 Slave offset low 8147 Slave offset high 8148 Protocol low 8149 Protocol high 814A Response low 814B Response high 814C Message high low 814D Message...

Page 111: ...IFO lower 815F Signal FIFO upper 8161 Trigger capture 8162 Clock control 8163 External trigger control 8164 Trigger interrupt enable 8380 Non volatile memory Address 8381 control Address 8382 Address 8383 Flash data 8384 SRAM data Table 20 I O Map Page B5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 112: ...EPC 7 Hardware Reference NOTES B B Page B6 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 113: ... performance disk controllers Installing a PC Add In Card Installation of an add in card is simple Follow the instructions below MAKE SURE THAT THE INSTALLATION PROCEDURE DESCRIBED HERE IS PERFORMED IN A STATIC FREE ENVIRONMENT Do not remove any modules from their anti static bags unless you are in a static free environment The EPC 7 and EPC7 AM modules like most other electronic devices are susce...

Page 114: ...7 AM assembly on a static free work surface with the EPC7 AM side up and the front panel to your left as shown in Figure C 1 below This will position the bottom of the assembly closest to you P1 Connector top Front Panel Figure C 1 EPC 7 EPC7 AM Orientation ÿ Remove the 8 side panel screws shown in Figure C 1 above Set these screws aside for now You will need them later ÿ If you are installing a f...

Page 115: ...crew shown in Figure C 3 below Slide the retainer clip up toward the top of the EPC7 AM as far as it will go top Front Panel PC Add in Card Thumbscrew Retainer Clip Install here Figure C 3 Inserting the PC Add In Card Page C3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 116: ...e to pass through the slot in the front of the EPC7 AM as shown in Figure C 3 C C ÿ Slide the add in card down so the care edge inserts into the card edge connector Make sure that the tab on the bottom of the metal add in card end plate seats into the retainer slot of the EPC7 AM as shown in Figure C 4 below Retainer Slot PC Add In Card EPC7 AM Front Panel Add In Card End Plate Tab Figure C 4 Cut ...

Page 117: ...in place Remove both screws Note that removing the screw on the bottom handle will cause the retainer slot on the inside of the front panel to fall off Refer to Figure C 4 above Next remove the four corner screws that hold the front panel to the top and bottom rails You can now remove the front panel itself and install the add in card as described earlier Once the add in card is in position and yo...

Page 118: ...EPC 7 Hardware Reference NOTES C C Page C6 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 119: ...BIOS 85 initialization 53 selftest 6 15 setup 15 23 block transfers 48 bus arbiter 32 Bus error 60 66 bus grant 82 bus grant signals 7 bus grant timeout 32 Bus release 53 Bus release mode 18 Bus timeout 5 32 63 Bus Timer function 32 Bus watching 27 byte order 46 byte ordering 45 59 byte swapping 44 46 Cache 27 49 CCS 28 CD ROM 13 28 chassis 9 Circuit board 34 CLK10 5 6 14 61 Clock 64 Clock control...

Page 120: ...le master access 54 EPC7 AM 20 EPConnect 43 47 68 EPROM 27 error messages 84 ESD shield 13 EVME bit 33 53 EXM configuration 18 installation 11 setup screen 19 EXM configuration error 85 EXM configuration register 31 53 EXM expansion interface 31 EXM 13A 12 EXM 2A 21 EXMbus 26 54 EXMID signal 31 53 External clock 14 64 External trigger register 14 33 38 64 External TTL trigger 38 64 Fast handshake ...

Page 121: ... endian 44 45 46 Location monitor 57 Lock 58 LOCK instruction prefix 49 74 Longword serial messages 58 63 low level formatting 24 not necessary 23 low level programming 68 LPT1 13 18 36 main setup screen 79 master 32 47 48 MDCF bit 26 54 MDFF bit 54 Memory 27 77 part numbers 77 Memory map 26 Memory mode register 28 54 memory parity interrupt 87 Memory Size error 79 memory upgrades 77 MEMS bits 26 ...

Page 122: ...Release on request 18 53 Request on no request 18 53 Reset bus accesses 54 interrupt 32 60 62 of registers 66 RSTP bit 32 56 soft 32 SYSRESET 62 watchdog timer 30 63 Resource manager 55 Response register 57 58 59 63 66 RMW cycle 49 74 ROM mapping 54 ROM shadowing 28 RONR 18 39 53 ROR 18 53 round robin 32 Round robin arbitration 18 53 RS 232 13 SBER bit 33 62 72 SCSI BIOS 28 54 connector 13 28 37 c...

Page 123: ... enable 56 System controller 5 18 32 system failure troubleshooting 82 Temperature 2 3 Test LED 56 TOD clock 29 88 89 TRIG connector 14 38 Trigger interrupt enable register 65 71 Trigger latch register 65 71 troubleshooting 81 TTL trigger drive register 33 61 TTL trigger latch register 64 TTL trigger sample register 60 ULA 62 63 67 Unique logical address 67 Unique logical address register 62 upgra...

Page 124: ...bus troubleshooting 83 VXI device type 4 fair requester mode 18 interface 31 local bus 11 61 manufacturer code 4 54 model code 4 protocols 4 registers 67 VXI expansion interface 38 VXI reset 75 VXR bit 32 33 62 66 watchdog timer 30 33 60 63 73 76 setup 30 Windows 16 Word serial messages 58 Write ready 57 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 125: ...Index I 7 I I Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 126: ...Index I 8 I I Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 127: ...I 5 I I Index Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 128: ...Index I 6 I I NOTES Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 129: ...Index I 7 I I Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 130: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

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