
VXIbus Interface
5. Set register 8130 with the value corresponding to bits 21-16 of the VMEbus
address with the two low order bits of the register set to 0.
VMEbus Address bits 21-16
Res
Res
6. Map the address.
7. Write the data
Microsoft C code for Example 2 -
LWORD addr; /* 32-bit A32 address */
BYTE data;
BYTE far * wptr;
outp(0x8102,(inp(0x8102)|2));
/* set VME access bit */
outp(0x8150,(WORD)(addr >> 24)); /* A31-A24 */
outp(0x8151,2 | (((addr << 8) >> 30) << 6));
/* A23-A22 and address modifier for A32 supervisory data access */
outp(0x8130,(WORD)((addr << 10) >> 24); /* A21-A16 */
wptr = (BYTE far *) (0xE00 (addr & 0X0000FFFFL));
*wptr = data; /* Write through window */
The success of the access can be checked either by enabling BERR as an interrupt or
by looking at the BERR bit in the event state register (8154) after each access. Since
writes are pipelined, software that looks at the BERR bit should first wait until the
DONE bit is set.
7
7
VXIbus Interrupt Handler
Although software available for the EPC-7 shields the user from the details of
interrupt handling, the following information is provided for the reader who needs
further detail.
The relationship between VME/VXI interrupts (and other interrupt-causing events)
and an interrupt as seen by a program is shown in the following diagram.
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