EPC-7 Hardware Reference
MLCK This EPC-7 specific bit is used for synchronization of messages from multi-
ple senders, something not provided for in the VXI specification. If 1, the
message register can be locked for the sending of a message. If 0, the mes-
sage register has been locked.
WRCP This EPC-7 specific bit is a read-only copy of the WRDY bit.
FSIG
Defined only when SIG=1, in which case FSIG is the number (0 or 1) of the
register in the FIFO holding the earliest signal.
LSIG
Defined only when SIG=1, in which case LSIG is the number (0 or 1) of the
register in the FIFO holding the most recent signal.
FSIG and LSIG have no utility to software. They exist as read-only bits for tests of
the EPC-7 during manufacture.
The bits RRDY, WRDY, ABMH, and MLCK in the response register are altered by
hardware-detected conditions. A read from the message-low clears RRDY. A write
into all or the lower 8 bits of the message low register clears WRDY. A read or write
to all or the lower 8 bits of the message high register clears ABMH. A read of the
alternate response register clears MLCK if WRDY is set.
Message High Reg, lower
814C
Message High Reg, upper
814D
7
7
Message Low Reg, lower
814E
Message Low Reg, upper
814F
The message registers may be used to implement the VXI message protocols. The
message-low register is typically used as an incoming message register for word-
serial messages; the sender does D16 writes into it from the VXIbus. The message-
high register is an extension for 32-bit longword serial messages. An access to this
register in the A16 space on the VXIbus clears flag ABMH in the response register.
VME A31-24 Address Reg
8150
This register is one of several that supply the VXIbus address bits when the EPC-7
makes an access in its "E page." This register supplies address bits A31-A24.
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