
VXIbus Interface
Since the EPC-7 is a DC device (a device whose ULA can be assigned dynamically
by the resource manager), an initial write to this register address from the VXIbus
assigns a ULA to the EPC-7.
A32
If set (1), the EPC-7 is an A16/A32 device; otherwise it is an A16/A24
device. This is a read-only bit that is controlled by the device type register
8143 below.
7
7
Device
Type
Reg,
lower
1
1
1
0
1
1
1
1
8142
Device Type Reg, upper
0
Slave Size
1
0
0
0
S
8143
This register defines how much address space the EPC-7 consumes as a slave device,
and defines the EPC-7's VXI model code.
Slave size Only the high-order bit (bit 6) is writeable. Bit 5 takes on the value of bit
6. That is, the two encodings are 00 and 11. If 11, the EPC-7 responds
to a 16 MB range in the A32 space, and bit A32 in the ID register is set.
If 00, the EPC-7 responds to a 4 MB range in the A24 space, and bit A32
in the ID register is 0.
S
This read-only bit specifies if the EPC-7 has been jumpered as a slot-0
controller. 1 denotes no and 0 denotes yes. S forms part of the VXI
model code, which is 239 (S=0, denoting slot-0 controller) or 495 (S=1).
Status/Control Reg, lower
SRIE
1
SYSC
1
RDY
PASS
NOSF
RSTP
8144
Status/Control Reg, upper
SLE
MODI
SYSR
1
1
1
1
1
8145
This register contains VXI specified bits and EPC-7 device-dependent bits.
SLE
Slave enable. If set (1), the EPC-7 will respond to certain A24 or A32
accesses from the VXI data-transfer bus.
MODI If clear (0), it denotes that the EPC-7's MODID pin is being asserted.
SYSR SYSRESET. The EPC-7 asserts the VXI SYSRESET line while this bit is 1.
When using this bit, it is software's responsibility to ensure that the
VXI/VME specified minimum assertion time of SYSRESET is met. This bit
is read-only when accessing this register from the VXI A16 space.
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