EPC-7 Hardware Reference
15 8
7 0
Alternate Response Register
11111111
Copy of response register, lower
xx20
bits 7-0
LOCK
1
ABMH
SIG
MLCK
WRCP
FSIG
LSIG
The upper half of this register is 1111 1111 and the lower half is a read-only copy of
the lower half of the response register. The alternate response register is associated
with multiple senders of messages to the EPC-7 and the MLCK bit; reading this
register performs a test-and-set operation on MLCK if WRDY is set (WRDY in the
response register).
The protocol for synchronization of multiple senders of messages is as follows. A
sender must first read the alternate response register. If both WRCP (WRCP is a
copy of WRDY) and MLCK are set, the sender can send the message; otherwise the
sender must reread the alternate response register until this condition is true. For 16-
bit messages, the sender writes into the message low register. For 32-bit messages,
the sender must write into the message high register before writing into the message
low register.
Register State after Reset
7
7
A hardware reset of the EPC-7 (not a keyboard CTRL+ALT+DEL reset) clears all of
the register bits to 0 in the following registers (except those bits defined as a constant
1): 8130, 8150, 8151, 8158 bits 0-2, 815A, and 8163. This shuts down transfers to
the data-transfer bus and driving of trigger and interrupt lines. Also, during reset, bit
EVME in the battery backed register is masked off, the VXI reset condition (VXR) is
set, and the sticky BERR condition is masked on, which causes any outgoing VXI
data transfers to appear to complete with bus error without actually accessing the VXI
bus.
The BIOS clears the VME interrupt and event enable registers during initialization.
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