
Theory of Operation
•
Bits 0-2 of the interrupt generator register
•
TTL trigger drive register
•
External trigger register
•
VME A31-24 address register
•
VME A21-16 address register
•
VME modifier register
•
PASS and RDY bits in the status/control register
In addition, the VXR bit is set, the EVME bit is masked off, and the SBER bit is
masked on.
Assertion of the VXI SYSRESET signal when bit SRIE in the status/control register
is zero also places the EPC-7 in the soft reset state, except the PASS and RDY bits
are not cleared in this case.
Four conditions cause a full hardware reset of the EPC-7:
5
5
•
SYSRESET signal (when enabled in the status/control register)
•
Front-panel reset switch
•
Expiration of the watchdog timer when bit WDTR in the module
status/control register is set
•
Power
on
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