Phytec phyCORE-OMAP44 Series Hardware Manual Download Page 33

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phyCORE-OMAP44xx

Part I: PCM-049/phyCORE-OMAP44xx System on Module

L-760e_1 © PHYTEC Messtechnik GmbH 2012

55A

X_DISPC_DATA4

VCC_1V8_IO

DISPC data bit 4

56A

X_DISPC_DATA2

VCC_1V8_IO

DISPC data bit 2

57A

GND

Ground 0V

58A

X_DISPC_DATA0

VCC_1V8_IO

DISPC data bit 0

59A

X_DISPC_PCLK

VCC_1V8_IO

DISPC LCD pixel clock

60A

X_DISPC_DE

VCC_1V8_IO

DISPC data enable

configurable with J6

Pin Row X1B

Pin #

Signal

I/O

Description

X_KPD_COL1

VCC_1V8_IO

Keyboard column 1 (open drain)

X_KPD_COL2

VCC_1V8_IO

Keyboard column 2 (open drain)

X_KPD_ROW0

1.8 V

Keyboard row 0

GND

Ground 0V

X_KPD_COL4_CSI21_DX3

O/I

VCC_1V8_IO / CSI

Keyboard column 4 (open drain) /
CSI2-A (CSI21) differential data
lane positive input 3

X_KPD_ROW4_CSI21_DY3

1.8 V / CSI

Keyboard row 4 / CSI2-A (CSI21)
differential data lane negative
input 3

X_KPD_COL5_CSI21_DX4

O/I

VCC_1V8_IO / CSI

Keyboard column 5 (open drain) /
CSI2-A (CSI21) differential data
lane positive input 4

X_KPD_ROW5_CSI21_DY4

1.8 V / CSI

Keyboard row 5 / CSI2-A (CSI21)
differential data lane negative
input 4

GND

Ground 0V

10B

X_CAM_SHUTTER

VCC_1V8_IO

Mechanical shutter control signal

11B

X_CAM_GLOBAL_RESET

I/O

1.8 V / VCC_1V8_IO Camera sensor reset

12B

X_CAM_STROBE

VCC_1V8_IO

Camera flash activation trigger

13B

X_FREF_CLK1_OUT

VCC_1V8_IO

FREF clock 1 output

14B

GND

Ground 0V

15B

X_CSI21_DX2

CSI

CSI2-A (CSI21) differential data
lane positive input 2

Table 3:

Pin-out of the phyCORE-Connector X1, Row B

Pin Row X1A

Pin #

Signal

I/O

Description

Table 2:

Pin-out of the phyCORE-Connector X1, Row A

Summary of Contents for phyCORE-OMAP44 Series

Page 1: ...A product of a PHYTEC Technology Holding company phyCORE OMAP44xx Hardware Manual Document No L 760e_1 SOM Prod No PCM 049 xxx SOM PCB No 1347 1 CB Prod No PCM 959 CB PCB No 1348 2 Edition March 2012 ...

Page 2: ... PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing so Copyright 2012 PHYTEC Messtechnik GmbH D 55129 Mainz Rights includ...

Page 3: ...6 1 4 3 2Real Time Clock RTC 38 1 4 3 3Power Management 38 1 4 3 4External Battery Charging 39 1 4 3 5Voltage Level and Current Consumption Measuring 39 1 4 4Reference Voltages 40 1 5 System Configuration and Booting 41 1 6 System Memory 43 1 6 1LPDDR2 SDRAM U1 PoP Memory 43 1 6 2NAND Flash Memory U4 44 1 6 2 1NAND Flash Lock Control J4 44 1 6 3I2C EEPROM U2 45 1 6 3 1Setting the EEPROM Lower Addr...

Page 4: ...11 Display Interfaces 63 1 11 1Parallel Display Interface 64 1 11 2MIPI Display Serial Interface DSI 65 1 11 3High Definition Multimedia Interface HDMI 66 1 12 Camera Interfaces 67 1 12 1Primary Camera Interface CSI2 A CSI21 68 1 12 2Secondary Camera Interface CSI2 B CSI22 69 1 13 Keyboard Interface 70 1 14 User LEDs 71 1 15 Technical Specifications 73 1 16 Hints for Integrating and Handling the p...

Page 5: ...nnectivity to UART 1 TTL 103 2 1 3 3 2 Connectivity to UART 2 RS 232 103 2 1 3 3 3 Connectivity to UART 3 RS 232 103 2 1 3 4Ethernet Connectivity X9 105 2 1 3 5USB Host Connectivity X8 X12 X18 X19 106 2 1 3 6USB OTG Connectivity X7 108 2 1 3 7Display Touch Connectivity X12 X13 109 2 1 3 7 1 PDI Data Connector X12 110 2 1 3 7 2 PDI Power Connector X13 114 2 1 3 7 3 Touch Screen Connectivity 114 2 1...

Page 6: ...USBB2 Signal Mapping 146 2 1 3 21 3I2C Signal Mapping 147 2 1 3 21 4Primary Camera Interface CSI2 A CSI21 Signal Mapping 147 2 1 3 21 5SPI1 Signal Mapping 148 2 1 3 21 6SPI2 Signal Mapping 149 2 1 3 21 7UART1 Signal Mapping 149 2 1 3 21 8PMIC Signal Mapping 150 2 1 3 21 9USBC1 Signal Mapping 150 2 1 3 21 10Audio Speaker Mapping 150 2 1 3 21 11Control Signal Mapping 150 2 1 3 21 12Power Signal Mapp...

Page 7: ... U2 EEPROM I2C Address via J1 J2 and J3 45 Table 14 EEPROM Write Protection States via J5 45 Table 15 Location of SD MMC Card Interface Signals SDMMC1 47 Table 16 Location of SD MMC Card Interface Signals SDMMC5 48 Table 17 Location of the UART Signals 50 Table 18 Location of the USB OTG Signals 51 Table 19 Location of the USB Host Signals 51 Table 20 Location of the IC USB Host Signals 52 Table 2...

Page 8: ...nector X5 103 Table 48 Operation States of the RS 232 Transceiver MAX3380 104 Table 49 Possible Configurations of the MAX3380 RS 232 Transceiver 104 Table 50 Distribution of the USB Hub s U7 Ports 107 Table 51 PDI Display Data Connector X12 Signal Description 111 Table 52 Auxiliary Interfaces at PDI Data Connector X12 113 Table 53 PDI Power Connector X32 Signal Description 114 Table 54 DVI Connect...

Page 9: ...able 71 USBB2 Signal Mapping 146 Table 72 I2C Signal Mapping 147 Table 73 CSI21 Camera Signal Mapping 147 Table 74 SPI1 Signal Mapping 148 Table 75 SPI2 McASP Signal Mapping 149 Table 76 UART1 Signal Mapping 149 Table 77 PMIC Signal Mapping 150 Table 78 USBC1 Signal Mapping 150 Table 79 Audio Speaker Mapping 150 Table 80 System Signal Mapping 150 Table 81 Power Signal Mapping 151 Table 82 Signals ...

Page 10: ...phyCORE OMAP44xx PHYTEC Messtechnik GmbH 2012 L 760e_1 ...

Page 11: ...rier Board Overview of Connectors LEDs and Buttons top view 83 Figure 16 phyCORE OMAP44xx Carrier Board Overview of Connectors LEDs and Buttons bottom view 84 Figure 17 Typical Jumper Numbering Scheme 88 Figure 18 phyCORE OMAP44xx Carrier Board Jumper Locations top view 89 Figure 19 phyCORE OMAP44xx Carrier Board Jumper Locations bottom view 90 Figure 20 phyCORE OMAP44xx SOM Connectivity to the Ca...

Page 12: ...gure 38 GPIOs at Expansion Connector X5 130 Figure 39 User programmable LEDs 132 Figure 40 Extension Connectors X18 X19 133 Figure 41 Components supporting the SD MM Card interfaces at connector X10 and X11 top view 135 Figure 42 Components supporting the SD MM Card interfaces at connector X10 and X11 bottom view 135 Figure 43 Boot Mode Selection Switches S1 and S2 137 Figure 44 System Reset Butto...

Page 13: ...e Tables which describe jumper settings show the default position in bold blue text Text in blue italic indicates a hyperlink within or external to the document Click these links to quickly jump to the applicable URL part chapter table or figure References made to the phyCORE Connector always refer to the high density Samtec connector on the undersides of the phyCORE OMAP44xx System on Module Abbr...

Page 14: ...e carrier board Sx_y Switch y of DIP Switch Sx used in reference to the DIP Switch on the carrier board VBAT SOM standby voltage input Note The BSP delivered with the phyCORE OMAP44xx usually includes drivers and or software for controlling all components such as interfaces memory etc Therefore programming close to hardware at register level is not necessary in most cases For this reason this manu...

Page 15: ...your embedded design allows you to focus on hardware peripherals and firmware without expending resources to re invent microcontroller circuitry Furthermore much of the value of the phyCORE module lies in its layout and test Production ready Board Support Packages BSPs and Design Services for our hardware will further reduce your development time and risk and allow you to focus on your product exp...

Page 16: ...phyCORE OMAP44xx 4 PHYTEC Messtechnik GmbH 2012 L 760e_1 Ordering Information The part numbering of the phyCORE has the following structur ...

Page 17: ... POH power on hours for the OMAP44xx The OMAP44xx is a typical state of the art microcontroller It packs enormous processing power into a small space The space requirements of the circuitry are optimized through the use of POP package on package memory This generation of processors lets you benefit from the latest developments in consumer electronics These modern controllers are used in smartphone...

Page 18: ...ize software so that it automatically adjusts the clock frequency and voltage to the processing requirements of the application In addition we can send your typical application to Texas Instruments for calculation of the POH value for your particular scenario The more accurate your description in terms of duration and use pattern the more reliable the results of this calculation We will be glad to...

Page 19: ...phyCORE OMAP44xx L 760e_1 PHYTEC Messtechnik GmbH 2012 7 Practical example of mobile applications operating time 7 years ...

Page 20: ...phyCORE OMAP44xx 8 PHYTEC Messtechnik GmbH 2012 L 760e_1 ...

Page 21: ... PCM 049 phyCORE OMAP44xx System on Module Part 1 of this 2 part manual provides detailed information on the phyCORE OMAP44xx System on Module SOM designed for custom integration into customer applications The information in the following chapters is applicable to the 1347 1 PCB revision of the phyCORE OMAP44xx SOM ...

Page 22: ...Part I PCM 049 phyCORE OMAP44xx System on Module phyCORE OMAP44xx 10 PHYTEC Messtechnik GmbH 2012 L 760e_1 ...

Page 23: ...he Texas Instruments OMAP44xx microcontroller Its universal design enables its insertion in a wide range of embedded applications All controller signals and ports extend from the controller to high density pitch 0 5 mm connectors aligning two sides of the board allowing it to be plugged like a big chip into a target application Precise specifications for the controller populating the board can be ...

Page 24: ...in debug interface through JTAG connector Three I2 C interfaces One SPI interfaces Two SD MMC card interfaces with DMA I2S interface Multichannel audio serial interface McASP Keyboard interface with up to 6 rows and 6 columns Up to two LVDS camera interfaces Two user programmable LEDs Four dedicated GPIO IRQ ports additionally nearly all pins can be alternatively used as GPIOs Industrial temperatu...

Page 25: ...phyCORE OMAP44xx Part I PCM 049 phyCORE OMAP44xx System on Module L 760e_1 PHYTEC Messtechnik GmbH 2012 13 1 1 1 Block Diagram Figure 1 Block Diagram of the phyCORE OMAP44xx ...

Page 26: ...Part I PCM 049 phyCORE OMAP44xx System on Module phyCORE OMAP44xx 14 PHYTEC Messtechnik GmbH 2012 L 760e_1 1 1 2 View of the phyCORE OMAP44xx Figure 2 Top view of the phyCORE OMAP44xx controller side ...

Page 27: ...phyCORE OMAP44xx Part I PCM 049 phyCORE OMAP44xx System on Module L 760e_1 PHYTEC Messtechnik GmbH 2012 15 Figure 3 Bottom view of the phyCORE OMAP44xx connector side ...

Page 28: ...d at least the matching number of GND pins Corresponding GND X1 6C 11C 16C 21C 26C 6D 9D 14D 19D 24D Please refer to Section 1 2 for information on additional GND Pins located at the phyCORE Connector X1 Caution We recommend connecting all available 3V3 input pins to the power supply system on a custom carrier board housing the phyCORE OMAP44xx and at least the matching number of GND pins neighbor...

Page 29: ...RE Connector as well as the mating connector on the phyCORE OMAP44xx Carrier Board or target hardware thereby considerably reducing the risk of pin identification errors Since the pins are exactly defined according to the numbered matrix previously described the phyCORE Connector is usually assigned a single designator for its position X1 for example In this manner the phyCORE Connector comprises ...

Page 30: ...ecial attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller and other on board components Please refer to the Texas Instruments OMAP44xx Reference Manual for details on the functions and features of controller signals and port pins Note SL is short for Signal Level V and is the applicable logic level to interface a given pin Those pins marked...

Page 31: ...CSI2 B CSI22 differential data lane negative input 12A GND Ground 0V 13A X_CSI21_DX0 I CSI CSI2 A CSI21 differential clock positive input 14A X_CSI21_DY0 I CSI CSI2 A CSI21 differential clock negative input 15A X_CSI21_DX1 I CSI CSI2 A CSI21 differential data lane positive input 1 16A X_CSI21_DY1 I CSI CSI2 A CSI21 differential data lane negative input 1 17A GND Ground 0V 18A X_I2C4_SDA I O 1 8 V ...

Page 32: ...8 V ABE McASP auto mute input 40A X_McBSP3_DX I O 1 8 V VCC_1V8_IO ABE McBSP3 transmitted serial data 41A X_McASP_ACLKX O VCC_1V8_IO ABE McASP clock transmit 42A GND Ground 0V 43A X_DMTIMER9 I O 1 8 V VCC_1V8_IO DM timer event input or PWM output from pin AH24 of the OMAP44xx or USBB2_ULPITTL_CLK output from pin AG121 44A X_DISPC_DATA22 O VCC_1V8_IO DISPC data bit 22 45A X_DISPC_DATA20 O VCC_1V8_I...

Page 33: ...CSI21 differential data lane positive input 31 6B X_KPD_ROW4_CSI21_DY3 I 1 8 V CSI Keyboard row 4 CSI2 A CSI21 differential data lane negative input 31 7B X_KPD_COL5_CSI21_DX4 O I VCC_1V8_IO CSI Keyboard column 5 open drain CSI2 A CSI21 differential data lane positive input 41 8B X_KPD_ROW5_CSI21_DY4 I 1 8 V CSI Keyboard row 5 CSI2 A CSI21 differential data lane negative input 41 9B GND Ground 0V ...

Page 34: ...detection 28B X_McBSP3_CLKX I O 1 8 V VCC_1V8_IO ABE McBSP3 combined serial clock 29B GND Ground 0V 30B VCC_1V8_IO O 1 8 V IO reference voltage 31B X_SPI1_CS1 O VCC_1V8_IO McSPI1 chip select 1 32B X_SPI1_CS2 O VCC_1V8_IO McSPI1 chip select 2 33B X_SPI1_MOSI I O 1 8 V VCC_1V8_IO McSPI1 master output slave input 34B X_SPI1_CLK I O 1 8 V VCC_1V8_IO McSPI1 clock master output slave input 35B GND Groun...

Page 35: ..._1V8_IO DISPC data bit 1 58B X_DISPC_HSYNC O VCC_1V8_IO DISPC horizontal synchronization 59B X_DISPC_VSYNC O VCC_1V8_IO DISPC vertical synchronization 60B GND Ground 0V 1 configurable with JN1 Pin Row X1C Pin Signal I O SL Description 1C VCC_3V3_IN I Power 3 3 V Primary voltage supply input 2C VCC_3V3_IN I Power 3 3 V Primary voltage supply input 3C VCC_3V3_IN I Power 3 3 V Primary voltage supply ...

Page 36: ...thernet transmit positive output 25C X_ETH_TX O VCC_3V3_S Ethernet transmit negative output 26C GND Ground 0V 27C X_ETH_SPEED O VCC_3V3_S Ethernet Speed Indicator open drain 28C X_JTAG_TDO O VCC_1V8_IO JTAG test data output 29C X_JTAG_TMS I O 1 8 V VCC_1V8_IO JTAG test mode select 30C X_JTAG_TCK I 1 8 V JTAG test clock input 31C GND Ground 0V 32C X_JTAG_TDI I 1 8 V JTAG test data input 33C X_DPM_E...

Page 37: ...ial positive or negative1 49C X_DSI_DY2 O DSI DSI1 display lane 2 differential positive or negative1 50C GND Ground 0V 51C X_DSI1_DX4 O DSI DSI1 display lane 4 differential positive or negative1 52C X_DSI1_DY4 O DSI DSI1 display lane 4 differential positive or negative1 53C X_I2C1_SCL O VCC_1V8_IO I2C1 clock open drain 54C X_I2C1_SDA I O 1 8 V VCC_1V8_IO I2C1 data open drain 55C GND Ground 0V 56C ...

Page 38: ... 232 Serial transmit signal UART 3 12D X_UART3_RS232_RX I RS 232 Serial receive signal UART 3 13D X_UART2_TX O VCC_1V8_IO Serial transmit signal UART 2 14D GND Ground 0V 15D X_UART2_RX I 1 8 V Serial receive signal UART 2 16D X_UART4_TX O VCC_1V8_IO Serial transmit signal UART 4 17D X_UART4_RX I 1 8 V Serial receive signal UART 4 18D X_USBB1_OC_GPIO_120 I 1 8 V USB Host overcurrent signal input 19...

Page 39: ...l positive or negative1 40D X_HDMI_DATA2Y O HDI HDMI display data 2 differential positive or negative1 41D GND Ground 0V 42D X_SYS_NIRQ2 I 1 8 V External interrupt 43D X_FREF_CLK4_OUT O VCC_1V8_IO FREF clock 4 output 44D X_PMIC_CLK32KAUDIO O 1 8 V 32 kHz digital gated output clock for audio device 45D GND Ground 0V 46D X_DSI1_DX1 O DSI DSI1 display lane 1 differential positive or negative1 47D X_D...

Page 40: ...xternal charger status pin 57D X_BOOT1 I 1 8 V System boot configuration pin 1 58D X_BOOT3 I 1 8 V System boot configuration pin 3 59D GND Ground 0V 60D X_BOOT5 I 1 8 V System boot configuration pin 5 1 Can be configured by setting the appropriate control register Please refer to the OMAP44xx Reference manual for more information Pin Row X1D Pin Signal I O SL Description Table 5 Pin out of the phy...

Page 41: ...It shows their default positions and possible alternative positions and functions A detailed description of each solder jumper can be found in the applicable chapter listed in the table Figure 5 Typical Jumper Pad Numbering Scheme If manual jumper modification is required please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the ...

Page 42: ...Part I PCM 049 phyCORE OMAP44xx System on Module phyCORE OMAP44xx 30 PHYTEC Messtechnik GmbH 2012 L 760e_1 Figure 6 Jumper Locations top view ...

Page 43: ...phyCORE OMAP44xx Part I PCM 049 phyCORE OMAP44xx System on Module L 760e_1 PHYTEC Messtechnik GmbH 2012 31 Figure 7 Jumper Locations bottom view ...

Page 44: ...ill have this lock function PleaserefertothecorrespondingNANDmemorydatasheet for more detailed information 0R 0402 Section 1 6 2 1 1 2 or open NAND Flash U4 not locked 2 3 NAND Flash U4 locked J5 J5 connects pin 7 of the serial memory at U2 to GND On many memory devices pin 7 enables disables the activation of a write protect function It is not guaranteed that the standard serial memory populating...

Page 45: ... 13 Position 1 pins 1 2 4 5 7 8 and 10 11 connect pairwise Last 4 signals of the keyboard interface KPD_COL4 KPD_ROW4 KPD_COL5 KPD_ROW5 are connected to pins X1B5 to X1B8 Position 2 pins 2 3 5 6 8 9 and 11 12 connect pairwise Last 4 lanes of the primary camera interface CSI21_DX3 CSI21_DY3 CSI21_DX4 CSI21_DY4 extend to pins X1B5 to X1B8 1 This option is intend for applications without display but ...

Page 46: ...Part I PCM 049 phyCORE OMAP44xx System on Module phyCORE OMAP44xx 34 PHYTEC Messtechnik GmbH 2012 L 760e_1 ...

Page 47: ...C 5C 1D 2D 3D 4D 5D Connect all 3 3 V VCC input pins to your power supply and at least the matching number of GND pins Corresponding GND X1 6C 11C 16C 21C 26C 6D 9D 14D 19D 24D Please refer to Section 1 2 for information on additional GND Pins located at the phyCORE Connector X1 1 4 2 Backup Voltage VBAT To backup the RTC of the PMIC TWL6030 on the module a secondary voltage source of 3 3 V can be...

Page 48: ... Regulator Internally generated voltages VCC_CORE1 0 93 V 1 1 V VCC_CORE2 0 93 V 1 1 V VCC_CORE3 0 93 V 1 1 V VCC_1V8_IO 1 8 V VCC_MEM 1 2 V VCC_V1V29 1 2 V VCC_2V1 2 1 V VCC_CXIO 1 8 V VCC_DAC 1 8 V VCC_MMC1 3 V 1 8 V VCC_3V3_S 3 3 V VCC_PP 3 3 V VCC_USB_3V3 3 3 V VCC_CORE1 0 93 V 1 1 V OMAP44xx mpu VDD_MPU VCC_CORE2 0 93 V 1 1 V OMAP44xx iva audio VDD_IVA_AUDIO VCC_CORE3 0 93 V 1 1 V OMAP44xx co...

Page 49: ...phyCORE OMAP44xx Part I PCM 049 phyCORE OMAP44xx System on Module L 760e_1 PHYTEC Messtechnik GmbH 2012 37 Figure 8 Power Supply Diagram ...

Page 50: ...ion 1 All special functions of the PMIC such as RTC interrupts use of power groups etc require the PMIC to be programmed via I2 C inter face At the time of delivery only the generation of the required voltages is implemented Please refer to the TWL6030 Technical Ref Man for more information on how to program the PMIC Pin Signal name Connected to Description PMIC_PREQ1 OMAP44xx U1 signal SYS_PWR_RE...

Page 51: ... of the module Thus it is possible to monitor these values in software too The two voltages VCC_3V3 and VCC_1V8_IO can be measured by using the embedded general purpose ADCs GPADC2 and GPADC3 of the TWL6030 PMIC The current consumption of the module is converted to a proportional voltage by the Linear Technology current sense IC LT6106 U9 The resulting voltage can be measured by reading the value ...

Page 52: ...erence voltages are VCC_MMC1 and VCC_3V3_S VCC_MMC1 is needed because the MMC1 supply voltage can be switched between 1 8 V and the default 3 V by setting the corresponding register of the PMIC The MMC1 reference voltage is brought out at pin X1B18 VCC_3V3_S is the reference voltage of the switchable 3 3 V domain which provides the supply the voltages of the RS 232 transceiver the Ethernet control...

Page 53: ...rap in permanent memories such as NAND Flash or SD Cards and executes it Memory booting is normally applicable after a cold or a warm reset Please refer to the OMAP44xx Reference Manual for more information A configuration circuitry pull up and pull down resistors connected to sys_boot 7 0 is located on the phyCORE module so no further settings are necessary The boot configuration of pins sys_boot...

Page 54: ... MMC1 USB UART 111100 MMC2 multi plexed with MMC5 only dat0 3 USB Table 9 Boot Modes of the phyCORE OMAP44xx memory type devices preferred 1 1 Defaults are in bold blue text Boot Mode Selec tion X_BOOT 5 0 Booting Device Order 1st 2nd 3rd 4th 000011 USB NAND 000101 USB MMC1 001011 UART NAND 001101 UART MMC1 011001 USB UART MMC1 NAND 011010 UART MMC2 multi plexed with MMC5 only dat0 3 011011 USB UA...

Page 55: ... internal subdivided in two 32 bit wide LPDDR2 SDRAM dies The chip is connected to the special LPDRR2 interface called extended memory interface EMIF of the OMAP44xx processor The LPDDR2 SDRAM memory is accessed via the second AHB port starting at 0x8000 0000 Typically the LPDDR2 SDRAM initialization is performed by a boot loader or operating system following a power on reset and must not be chang...

Page 56: ...les and a data retention rate of 10 years The NAND Flash memory is connected to the GPMC bus 1 6 2 1 NAND Flash Lock Control J4 Jumper J4 controls the block lock feature of the NAND Flash U4 Setting this jumper to position 2 3 enables the block lock commands and protects or locks all blocks of the device while position 1 2 or removing this jumper will disable the block lock commands Block lock fea...

Page 57: ... A0 A1 and A2 The four upper address bits of the device are fixed at 1010 see CAT24WC32C data sheet The remaining three lower address bits of the seven bit I2 C are configurable using jumpers J1 J2 and J3 J2 sets address bit A0 J1 address bit A1 and J3 address bit A2 Table 13 below shows the resulting seven bit I2 C device address for the eight possible jumper configurations 1 6 3 2 EEPROM Write P...

Page 58: ...k GmbH 2012 L 760e_1 1 6 4 Memory Model There is no special address decoding device on the phyCORE OMAP44xx which means that the memory model is given according to the memory mapping of the OMAP44xx Please refer to the OMAP44xx Reference Manual for more information on the memory mapping ...

Page 59: ...s to switch VCC_MMC1 from 3 V default to 1 8 V VCC_MMC1 is also available as reference voltage on pin X1B18 of the phyCORE Connector Please consider the maximum load allowed for the reference voltage VCC_MMC1 to avoid any disfunction or damage of the module The maximum load is 150 mA Because of compatibility reasons a card detect signal X_PMIC_MMC1_CD is added to the SDMMC1 Card Interface This sig...

Page 60: ...a bit 1 X1B25 X_SDMMC5_DAT2 I O 1 8 V VCC_1V8_IO SDMMC5 data bit 2 X1B26 X_SDMMC15_DAT3 I O 1 8 V VCC_1V8_IO SDMMC5 data bit 3 Table 16 Location of SD MMC Card Interface Signals SDMMC5 Note The signal level of the SD MMC card interface SDMMC5 is 1 8 V Thus integration of an SD MMC card slot on custom target hardware requires level shifters supplied with VCC_1V8_IO X1B30 at one of the supply rails ...

Page 61: ...MAP44xx USB Host interchip interface 6 Auto MDIX enabled 10 100 Ethernet interface implemented with an Ethernet controller attached to the OMAP44xx GPMC interface 7 ThreeI2 C interfaces 8 One Serial Peripheral Interface SPI interface 9 One Multichannel buffered serial port McBSP interface 10 One Multichannel audio serial port McASP interface The following sections of this chapter detail each of th...

Page 62: ...be removed and 0 Ohm resistor network RN1 can be populated In this configuration there is a direct short between the TTL level signal name e g UART3_RX and RS 232 level signal name e g X_UART3_RS232_RX leaving the RS 232 level signal names operating at TTL levels The following table shows the location of the signals on the phyCORE Connector Pin Signal I O SL Description X1C10 X_UART1_TX O VCC_1V8_...

Page 63: ... have an overcurrent input this signal is connected to GPIO 120 of the OMAP44xx The USB3320 USB High Speed transceiver U8 is supplied by the switchable 3 3 V voltage domain VCC_3V3_S which is also available at the reference voltage output pin X1D23 on the phyCORE Connector To fully support VBUS power control using an external VBUS switch the phyCORE OMAP44xx provides the control signal X_USBB1_PWR...

Page 64: ...s 1 8 5 1 Ethernet Controller U12 With an Ethernet controller mounted at U12 the phyCORE OMAP44xx has been designed for use in 10Base T and 100Base T networks The 10 100Base T interface with its LED signals extends to phyCORE Connector X1 The Ethernet controller s integrated PHY supports HP Auto MDIX technology eliminating the need for the consideration of a direct connect LAN cable or a cross ove...

Page 65: ...are already populated on the module Connection to an external Ethernet magnetics should be done using very short signal traces The TPI TPI and TPO TPO signals should be routed as 100 Ohm differential pairs The same applies for the signal lines after the transformer circuit The carrier board layout should avoid any other signal lines crossing the Ethernet signals If a power management is implemente...

Page 66: ...evices to the first I2C module of the OMAP44xx the addresses of the on board I2C devices must be considered Table 23 lists the addresses already in use The addresses of the EEPROM can be configured by jumpers The table shows only the default addresses Please refer to Section 1 6 3 1 for alternative address settings Pin Signal I O SL Description X1C53 X_I2C1_SCL O VCC_1V8_IO I2C1 clock open drain X...

Page 67: ...onnected A D and D A devices such as Inter IC sound I2S compliant devices pulse code modulation PCM devices and time devision multiplexed TDM bus devices The OMAP44xx controller offers four instances of the McBSP module The interface signals of the third module McBSP3 are brought out to the phyCORE Connector The following table shows the location of the McBSP signals on the phyCORE Connector Pin S...

Page 68: ...y connect to a Sony Philips digital interface S PDIF transmit physical layer component The McASP module operates in transmit mode only it has no receive capabilities Pin Signal I O SL Description X1A35 X_McASP_AXR O VCC_1V8_IO ABE McASP serial data IO X1A36 X_McASP_AFSX O VCC_1V8_IO ABE McASP frame synchro nization transmit X1B37 X_McASP_AHCLKX O VCC_1V8_IO ABE McASP high frequency clock output X1...

Page 69: ...OMAP44xx As can be seen in the table above the voltage level is VCC_1V8_IO To avoid mismatch of different voltage levels external devices connected to these pins should be supplied by the reference voltage VCC_1V8_IO The IO reference voltage VCC_1V8_IO is available at X1B30 refer to Section 1 4 4 Alternatively an open drain circuit with a pull up resistor attached to VCC_1V8_IO can be connected to...

Page 70: ...Part I PCM 049 phyCORE OMAP44xx System on Module phyCORE OMAP44xx 58 PHYTEC Messtechnik GmbH 2012 L 760e_1 ...

Page 71: ...RE OMAP44xx to a standard emulator The JTAG Emulator adapter extends the signals of the module s JTAG connector to a standard ARM connector with 2 mm pin pitch The JA 002 therefore functions as an adapter for connecting the module s non ARM compatible JTAG connector X7 to standard Emulator connectors Note The JTAG connector X7 only populates phyCORE OMAP44xx modules with order code PCM 049 xxxxxxx...

Page 72: ...V VCC_1V8_IO JTAG test mode select X1C30 X_JTAG_TCK I 1 8 V JTAG test clock input X1D31 X_JTAG_nTRST I 1 8 V JTAG test reset X1C32 X_JTAG_TDI I 1 8 V JTAG test data input X1D32 X_JTAG_RTCK O VCC_1V8_IO JTAG ARM clock emulation X1C33 X_DPM_EMU1 I O 1 8 V VCC_1V8_IO Debug pin manager pin 1 X1D33 X_DPM_EMU0 I O 1 8 V VCC_1V8_IO Debug pin manager pin 0 Table 29 Location of the JTAG Signals on the phyC...

Page 73: ...phyCORE OMAP44xx Part I PCM 049 phyCORE OMAP44xx System on Module L 760e_1 PHYTEC Messtechnik GmbH 2012 61 Figure 9 JTAG Interface at X7 top view ...

Page 74: ...Part I PCM 049 phyCORE OMAP44xx System on Module phyCORE OMAP44xx 62 PHYTEC Messtechnik GmbH 2012 L 760e_1 Figure 10 JTAG Interface at X7 bottom view ...

Page 75: ...stem on Module L 760e_1 PHYTEC Messtechnik GmbH 2012 63 1 11 Display Interfaces The phyCORE OMAP44xx provides three different display interfaces 1 Parallel Display Interface 2 MIPI Display Serial Interface DSI 3 High Definition Multimedia Interface HDMI ...

Page 76: ...8_IO DISPC data bit 17 X1A48 X_DISPC_DATA16 O VCC_1V8_IO DISPC data bit 16 X1B48 X_DISPC_DATA15 O VCC_1V8_IO DISPC data bit 15 X1A49 X_DISPC_DATA14 O VCC_1V8_IO DISPC data bit 14 X1B49 X_DISPC_DATA13 O VCC_1V8_IO DISPC data bit 13 X1A50 X_DISPC_DATA12 O VCC_1V8_IO DISPC data bit 12 X1B50 X_DISPC_DATA11 O VCC_1V8_IO DISPC data bit 11 X1A51 X_DISPC_DATA10 O VCC_1V8_IO DISPC data bit 10 X1B52 X_DISPC...

Page 77: ...gured by setting the appropriate control register Please refer to the OMAP44xx Reference manual for more information X1C47 X_DSI1_DY0 O DSI DSI1 display lane 0 differential positive or negative 1 X1D46 X_DSI1_DX1 O DSI DSI1 display lane 1 differential positive or negative1 X1D47 X_DSI1_DY1 O DSI DSI1 display lane 1 differential positive or negative 1 X1C48 X_DSI1_DX2 O DSI DSI1 display lane 2 diff...

Page 78: ..._DDC_SDA I O 1 8 V VCC_1V8_IO HDMI display data channel data open drain X1C37 X_HDMI_DATA0X O HDMI HDMI display data 0 differential positive or negative 1 1 Can be configured by setting the appropriate control register Please refer to the OMAP44xx Reference manual for more information X1C38 X_HDMI_DATA0Y O HDMI HDMI display data 0 differential positive or negative1 X1D37 X_HDMI_DATA1X O HDMI HDMI ...

Page 79: ...SI22 The control signals shown in the following table can be used for both camera interface independently Please refer to the Texas Instruments OMAP44xx Reference Manual for more information Pin Signal I O SL Description X1B10 X_CAM_SHUTTER O VCC_1V8_IO Mechanical shutter control signal X1B11 X_CAM_GLOBAL_RESET I O 1 8 V VCC_1V8_IO Camera sensor reset X1B12 X_CAM_STROBE O VCC_1V8_IO Camera flash a...

Page 80: ...21_DY2 I CSI CSI2 A CSI21 differential data lane negative input 2 X1B5 X_KPD_COL4_CSI21_DX3 O I VCC_1V8_IO CSI Keyboard column 4 open drain CSI2 A CSI21 differential data lane posi tive input 3 see note below X1B6 X_KPD_ROW4_CSI21_DY3 I 1 8 V CSI Keyboard row 4 CSI2 A CSI21 differential data lane negative input 3 see note below X1B7 X_KPD_COL5_CSI21_DX4 O I VCC_1V8_IO CSI Keyboard column 5 open dr...

Page 81: ...CCP2 v1 0 The following table shows the location of the applicable interface signals of the secondary camera interfaces on the phyCORE Connector Pin Signal I O SL Description X1A8 X_CSI22_DX0 I CSI CSI2 B CSI22 differential clock lane positive input X1A9 X_CSI22_DY0 I CSI CSI2 B CSI22 differential clock lane negative input X1A10 X_CSI22_DX1 I CSI CSI2 B CSI22 differential data lane positive input ...

Page 82: ...w 2 X1A6 X_KPD_ROW3 I 1 8 V Keyboard row 3 X1B5 X_KPD_COL4_CSI21_DX3 O I VCC_1V8_IO CSI Keyboard column 4 open drain CSI2 A CSI21 differential data lane positive input 3 see note below X1B6 X_KPD_ROW4_CSI21_DY3 I 1 8 V CSI Keyboard row 4 CSI2 A CSI21 differential data lane negative input 3 see note below X1B7 X_KPD_COL5_CSI21_DX4 O I VCC_1V8_IO CSI Keyboard column 5 open drain CSI2 A CSI21 differe...

Page 83: ...1 PHYTEC Messtechnik GmbH 2012 71 1 14 User LEDs The phyCORE OMAP44xx provides two user LEDs on board a red D2 and a green D3 The LEDs can be controlled by setting GPIO 152 D2 and GPIO 153 D3 to the desired output level A high level turns the LED on a low level turns it off ...

Page 84: ...Part I PCM 049 phyCORE OMAP44xx System on Module phyCORE OMAP44xx 72 PHYTEC Messtechnik GmbH 2012 L 760e_1 ...

Page 85: ... 11 The module s profile is max 5 0 mm thick with a maximum component height of 1 5 mm on the bottom connector side of the PCB and approximately 2 0 mm on the top microcontroller side The board itself is approximately 1 5 mm thick Figure 11 Physical Dimensions Note To facilitate the integration of the phyCORE OMAP44xx into your design the footprint of the phyCORE OMAP44xx is available see also Sec...

Page 86: ...ce between the two connected PCBs when the module is mounted on the corresponding carrier board In order to get the exact spacing the maximum component height 1 5 mm on the bottom side of the phyCORE must be subtracted Please refer to the corresponding data sheets and mechanical specifications provided by Samtec www samtec com Dimensions 51 mm x 41 mm Weight approximately 16 g with all optional co...

Page 87: ...aq faq phyCORE OMAP44xx html or http www phytec eu europe support faq faq phyCORE OMAP44xx html the link Carrier Board within the category Dimensional Drawing leads to the layout data as shown in Figure 12 It is available in different file formats different support packages are available to support you in all stages of your embedded development Please visit http www phytec de de support support pa...

Page 88: ...Part I PCM 049 phyCORE OMAP44xx System on Module phyCORE OMAP44xx 76 PHYTEC Messtechnik GmbH 2012 L 760e_1 Figure 12 Footprint of the phyCORE OMAP44x ...

Page 89: ...phyCORE OMAP44xx Part I PCM 049 phyCORE OMAP44xx System on Module L 760e_1 PHYTEC Messtechnik GmbH 2012 77 1 17 Component Placement Diagram Figure 13 phyCORE OMAP44xx Component Placement top view ...

Page 90: ...Part I PCM 049 phyCORE OMAP44xx System on Module phyCORE OMAP44xx 78 PHYTEC Messtechnik GmbH 2012 L 760e_1 Figure 14 phyCORE OMAP44xx Component Placement bottom view ...

Page 91: ...nd all board images in the following chapters are applicable to the 1348 2 PCB revision of the phyCORE OMAP44xx Carrier Board The carrier board can also serve as a reference design for development of custom target hardware in which the phyCORE SOM is deployed Carrier Board schematics with BoM are available under a Non Disclosure Agreement NDA Re use of carrier board circuitry likewise enables user...

Page 92: ...Part II PCM 959 phyCORE OMAP44xx Carrier Board phyCORE OMAP44xx 80 PHYTEC Messtechnik GmbH 2012 L 760e_1 ...

Page 93: ...4xx at RS 232 level Four USB Host interfaces available at a standard USB A connector as well as at the display and PEB connectors USB OTG interface brought out to a standard USB Mini AB connector 10 100 Mbps Ethernet interface with Power over Ethernet Complete Audio interface available at three 3 5 mm audio jacks Phytec Display Interface PDI LVDS display interface with separate connectors for data...

Page 94: ...sequent programming of the phyCORE System on Module The carrier board design allows easy connection of additional expansion boards featuring various functions that support fast and convenient prototyping and software evaluation This modular development platform concept includes the following components the phyCORE OMAP44xx module populated with the OMAP44xx processor and all applicable SOM circuit...

Page 95: ... Figure 15 and Figure 16 It is equipped with the compo nents and peripherals listed in Table 37 Table 38 Table 40 and Table 41 For a more detailed description of each peripheral refer to the appropriate chapter listed in the applicable table Figure 15 and Figure 16 highlight the location of each peripheral for easy identification Figure 15 phyCORE OMAP44xx Carrier Board Overview of Connectors LEDs...

Page 96: ...Part II PCM 959 phyCORE OMAP44xx Carrier Board phyCORE OMAP44xx 84 PHYTEC Messtechnik GmbH 2012 L 760e_1 Figure 16 phyCORE OMAP44xx Carrier Board Overview of Connectors LEDs and Buttons bottom view ...

Page 97: ...ector RJ45 with speed and link led Section 2 1 3 4 X10 Secure Digital Memory MultiMedia Card slot Section 2 1 3 16 X11 Secure Digital Memory MultiMedia Card slot Section 2 1 3 16 X12 Display data connector Section 2 1 3 7 1 X13 Display Backlight supply voltage connector Section 2 1 3 7 2 X14 Headphone output connector Stereo Line Out connector 3 5 mm audio jack Section 2 1 3 10 X15 Stereo Micropho...

Page 98: ...at the phyCORE Connector to VCC3V3 3 3 V by level shifters on the phyCORE Carrier Board Ensure that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller User s Manual Data Sheets As damage from improper connections varies according to use and application it is the user s responsibility to take ...

Page 99: ... led D21 green Downstream port 1 USB1 green led D22 green Downstream port 4 USB4 green led D23 yellow Downstream port 1 USB1 amber led D27 green Indicates presence of VBUS at the USB OTG interface Section 2 1 3 6 D14 green VCC_1V8 1 8 V supply voltage Section 2 1 3 2 D15 green VCC_1V2 1 2 V supply voltage for the DSI2LVDS Bridge Chip D16 green VCC_3V3 3 3 V supply voltage for the phyCORE OMAP44xx ...

Page 100: ...s it is advisable to consult the applicable section in this manual for setting the associated jumpers Figure 17 Typical Jumper Numbering Scheme Table 41 provides a comprehensive list of all carrier board jumpers The table only provides a concise summary of jumper descriptions For a detailed description of each jumper see the applicable chapter listed in the right hand column of the table If manual...

Page 101: ...phyCORE OMAP44xx Part II PCM 959 phyCORE OMAP44xx Carrier Board L 760e_1 PHYTEC Messtechnik GmbH 2012 89 Figure 18 phyCORE OMAP44xx Carrier Board Jumper Locations top view ...

Page 102: ...Part II PCM 959 phyCORE OMAP44xx Carrier Board phyCORE OMAP44xx 90 PHYTEC Messtechnik GmbH 2012 L 760e_1 Figure 19 phyCORE OMAP44xx Carrier Board Jumper Locations bottom view ...

Page 103: ...ion 2 1 3 2 open VCC_1V8 enabled closed VCC_1V8 disabled JP3 Jumper JP3 enables the DC DC converter for the VCC_1V2 supply voltage Section 2 1 3 2 open VCC_1V2 enabled closed VCC_1V2 disabled JP4 Jumper JP4 enables the DC DC converter for the VCC_5V supply voltage Section 2 1 3 2 open VCC_5V enabled closed VCC_5V disabled JP5 Jumper JP5 enables DC DC converter for the the VCC_3V3 supply voltage Se...

Page 104: ...mper JP11 enables the bus transceiver of the first phyCAM P camera interface Camera_1 at connector X20 For future derivatives of the phyCORE OMAP44xx open Bus transceiver disabled first phyCAM P interface Camera_1 not available closed Bus transceiver enabled first phyCAM P interface Camera_1 can be used JP12 Jumper JP12 selects either 8 bit or 10 bit resolution of the first phyCAM P camera interfa...

Page 105: ...X14 J3 In combination with jumpers J4 and J8 and resistors R25 and R26 jumper J3 allows to configure the various operating modes of the RS 232 transceiver at U2 J3 connects the Force On input of the RS 232 transceiver to pad 2 of jumper J8 for further configuration Section 2 1 3 3 2 open FORCEON disconnected from jumper J8 and pulled HIGH by R25 closed FORCEON connected to jumper J8 J4 In combinat...

Page 106: ...d R26 1 2 Depending on the configuration of jumpers J3 and J4 FORCEON or FORECOFF or both inputs are connected to the Invalid output of the RS 232 driver 2 3 Depending on the configuration of jumpers J3 and J4 FORCEON or FORECOFF or both inputs are connected to GND_RS232 J9 Jumper J9 configures the I2C address of the touch screen controller at U41 Section 2 1 3 7 3 1 2 I2C device address set to 0x...

Page 107: ... phyCORE OMAP44xx pin X_FREF_CLK4_REQ or an oscillator at OZ1 on the carrier board Section 2 1 3 10 1 2 Pin MCLK of the audio codec connected to oscillator OZ1 19 2 MHz 2 3 Pin MCLK of the audio codec connected to X_FREF_CLK4_REQ X1D29 of the phyCORE OMAP44xx J14 Jumper J14 configures the source for the master clock at the phyCAM P interface connector X4 The clock can be generated either on the ph...

Page 108: ...CORE OMAP44xx SOM Connectivity to the Carrier Board Connector X22 on the carrier board provides the phyCORE System on Module connectivity The connector is keyed for proper insertion of the SOM Figure 20 above shows the location of connector X22 along with the pin numbering scheme as described in Section 1 2 Please refer to Section 1 15 for information on manufacturer part number and ordering Cauti...

Page 109: ... used as power on off signal input to allow for an ON OFF switch on a front panel X1B36 X_ABE_CLKS O VCC_1V8_IO GPIO 118 used as display enable signal at display data connector X12 X1B39 X_GPIO_114 I VCC_1V8_IO SPI Interface Ready signal X1D16 X_UART4_TX I 1 8 V GPIO 156 used as interrupt input of PEB connector X18 X1D17 X_UART4_RX I 1 8 V GPIO 155 used as interrupt input of PEB connector X19 X1D2...

Page 110: ...t components of the system The following table lists the 5 voltage domains and their main use Voltage domain Description VCC_12_24 Main supply voltage from wall adapter input at X6 or Power of Ethernet 12 V to 24 V DC at X9 VCC_5V 5 V voltage domain required for different interfaces such as USB HDMI etc VCC_3V3 3 3 V voltage domain supplying the phyCORE OMAP44xx and various peripherals VCC_5V_FIX ...

Page 111: ...are as well as whether an optional expansion board is connected to the carrier board An adapter with a minimum supply of 2 0 A is recommended Figure 22 Power Connector Corresponding to Wall Adapter Input X6 It is necessary to ensure that jumper JP5 is open in order to supply power to the phyCORE module LEDs Color Description D17 green VCC_5V 5 V supply voltage D16 green VCC_3V3 3 3 V supply voltag...

Page 112: ...ave to be done 1 Plug in the power supply connector The power LEDs D14 D17 should light up and the phyCORE sends serial data from UART3 to the top DB 9 sub connector of connector P1 2 For powering down the phyCORE OMAP44xx button S3 should be pressed for a minimum time of 10 s 3 To restart the system press button S3 for approx 2 s All power LEDs should light up again and the phyCORE sends serial d...

Page 113: ...s current access measurement points To calculate the current draw the resulting voltage drop across the shunt resistors must be measured Table 46 lists the voltage domains and the associated shunt resistors as well as the resistor values The shunt resistors chosen are small enough to not affect the output voltage it will be reduced by the voltage drop across the shunt but large enough to have a di...

Page 114: ...ORE OMAP44xx Carrier Board provides connectivity to three of the four universal asynchronous interfaces of the phyCORE OMAP44xx The signals of UART2 and UART3 are available on the Dual Port Connector P1 at RS 232 level whereas the signals of UART1 are brought out on the expansion connector X5 at TTL level Figure 24 shows the signal mapping of the two female DB 9 connectors at connector P1 Figure 2...

Page 115: ...on for 30 seconds on either the receiver or transmitter inputs The signal inputs FORCEON and FORCEOFF together with the INVALID output signal control the different operation states of the MAX3380 as can be seen in Table 48 Jumpers J3 J4 and J8 as well as resistors R25 and R26 allow to configure the MAX3380 transceiver for the various operation modes Table 49 shows the required settings 2 1 3 3 3 C...

Page 116: ...wn INVALID INVALID Yes X Active Active Shutdown AutoShutdown INVALID INVALID No X High Z Active Table 48 Operation States of the RS 232 Transceiver MAX3380 Operation Mode R25 R26 J3 J4 J8 Shutdown Forced Off no matter not mounted not mounted mounted 2 3 Normal Operation Forced On mounted mounted not mounted not mounted not mounted Normal Operation AutoShutdown Plus shutdown after 30 s without rece...

Page 117: ...The LEDs for LINK green and SPEED yellow indication are integrated in the connector The required termination resistors for the Ethernet interface are assembled on the phyCORE OMAP44xx The Ethernet circuit includes a protective circuit to avoid a reverse current over the terminating resistors if the Ethernet controller s supply voltage VCC_3V3_S is turned off by the power management on the phyCORE ...

Page 118: ... ports One port extends to the standard USB connector X8 USB A The remaining ports are accessible at the display data connector X121 as well as on the PEB connectors X18 and X192 The latter three interfaces provide only data lines D and D They do not feature a supply line Vbus LEDs D19 to D23 as well as D5 and D10 signal use of the USB host interfaces Table 40 shows the assignment of the LEDs to t...

Page 119: ...EC Messtechnik GmbH 2012 107 USB Hub Port Connector Connector Type LED USB4 X12 40 pin FCC pins 16 D and 17 D D22 USB3 X18 20 pin header Row pins 19 D and 20 D D19 USB2 X19 20 pin header Row pins 19 D and 20 D D20 USB1 X8 USB A D21 Table 50 Distribution of the USB Hub s U7 Ports ...

Page 120: ...nal USB_OTG_OC to pin X1D42 X_SYS_NIRQ2 GPIO183 of the phyCORE OMAP44xx making it possible to evaluate this signal An overcurrent is detected if this signal is LOW Removing jumper J5 allows to utilize GPIO 183 of the OMAP44xx for other purpose Jumper JP9 configures the OTG operating mode By default this jumper is open which leaves the USB_OTG_ID pin floating and thus configuring the OTG interface ...

Page 121: ...959 phyCORE OMAP44xx Carrier Board L 760e_1 PHYTEC Messtechnik GmbH 2012 109 2 1 3 7 Display Touch Connectivity X12 X13 Figure 28 Display Touch Connectivity X12 X13 top view Figure 29 Display Touch Connectivity X12 X13 bottom view ...

Page 122: ...4xx After the signals from either display interface are converted to LVDS two multiplexer at U51 and U52 forward the LVDS signals to the PDI data connector Jumper JP13 allows to select which data is forwarded If jumper JP13 is open PDI data connector X12 provides the display signals from the parallel display interface of the phyCORE OMAP44xx see Section 1 11 1 These signals are converted into LVDS...

Page 123: ...I1_MOSI_3V3 O I 3 3 V SPI 1 master data out slave data in 4 SPI1_CS2_3V3 O 3 3 V SPI 1 chip select display adapter 5 DISP_IRQ I 3 3 V SPI interrupt input connected to GPIO 64 of the OMAP44xx X1D34 on the phyCORE Connector 6 VCC_3V3 O 3 3 V Logic supply voltage1 7 I2C4_SCL_3V3 I O 3 3 V I2C clock signal 8 I2C4_SDA_3V3 I O 3 3 V I2C data signal 9 GND Ground 10 LS_BRIGHT O 3 3 V PWM brightness contro...

Page 124: ... 28 DISP_LVDS_3 O 3 3 V LVDS data channel 3 negative output 29 DISP_LVDS_3 O 3 3 V LVDS data channel 3 positive output 30 GND Ground 31 DISP_LVDS_CLK O 3 3 V LVDS clock channel negative output 32 DISP_LVDS_CLK O 3 3 V LVDS clock channel positive output 33 GND Ground 34 TS_X I O 3 3 V Touch 35 TS_X I O 3 3 V Touch 36 TS_Y I O 3 3 V Touch 37 TS_Y I O 3 3 V Touch 38 n c not connected 39 GND Ground 40...

Page 125: ...C9 on the phyCORE Connector and to GPIO 181 X1B13 on the phyCORE Connector of the OMAP44xx DISP_ENA Can be used to enable or disable the display or to shutdown the backlight DISP_ENA is connected to GPIO 118 X1B36 on the phyCORE Connector of the OMAP44xx LS_BRIGHT PWM output to control the brightness of a display s backlight 0 dark 100 bright This signal is connected to the phyCORE s X_DMTIMER9_PW...

Page 126: ... to Table 41 An additional interrupt output is connected to GPIO 117 X1A39 on the phyCORE Connector of the OMAP44xx Pin Signal I O SL Description 1 GND Ground 2 VCC_3V3 O 3 3 V 3 3 V power supply display 3 GND Ground 4 VCC_5V O 5 V 5 V power supply display 5 GND Ground 6 VCC_5V O 5 V 5 V power supply display 7 GND Ground 8 VCC_5V O 5 V 5 V power supply display 9 GND Ground 10 LS_BRIGHT O 3 3 V PWM...

Page 127: ...h definition digital video format The HDMI interface brought out at DVI female connector X23 on phyCORE OMAP44xx Carrier Board comprises the following signal groups three pairs of data signals one pair of clock signals an I2C bus which is exclusively for the HDMI interface and the hot plug detect HPD signal Level shifters shift the I2 C interface signals and the hot plug detect signal from the IO ...

Page 128: ...nel 1 negative output 10 X_HDMI_DATA1Y O HDMI HDMI data channel 1 positive output 11 GND Ground 12 NC not connected 13 NC not connected 14 VCC_5V O 5 V 5V power supply 15 GND Ground 16 HDMI_HPD I 5 V HDMI hot plug detection 17 X_HDMI_DATA0X O HDMI HDMI data channel 0 negative output 18 X_HDMI_DATA0Y O HDMI HDMI data channel 0 positive output 19 GND Ground 20 NC not connected 21 NC not connected 22...

Page 129: ... Part II PCM 959 phyCORE OMAP44xx Carrier Board L 760e_1 PHYTEC Messtechnik GmbH 2012 117 S1 PE Earth S2 PE Earth S3 PE Earth S4 PE Earth S5 PE Earth S6 PE Earth Pin Signal I O SL Description Table 54 DVI Connector X23 ...

Page 130: ...I PCM 959 phyCORE OMAP44xx Carrier Board phyCORE OMAP44xx 118 PHYTEC Messtechnik GmbH 2012 L 760e_1 2 1 3 9 Camera Interfaces X4 X5 Figure 31 Camera Interfaces top view Figure 32 Camera Interfaces bottom view ...

Page 131: ...21 differential clock positive input X5C19 X_CSI21_DY0 I CSI CSI2 A CSI21 differential clock negative input X5C20 X_CSI21_DX1 I CSI CSI2 A CSI21 differential data lane positive input 1 X5C21 X_CSI21_DY1 I CSI CSI2 A CSI21 differential data lane negative input 1 X5C22 X_CSI21_DX2 I CSI CSI2 A CSI21 differential data lane positive input 2 X5C23 X_CSI21_DY2 I CSI CSI2 A CSI21 differential data lane n...

Page 132: ...amera module s Power Voltage Set output input CAM 2_VSET on camera connector X4 To attach the supply voltage to the Camera_2 interface circuitry jumper JP1 must be closed Note Pins X1B5 to X1B8 on the phyCORE Connector provide either signals of the keyboard interface or camera lanes 3 and 4 of the primary camera interface The resistor array JN1 on the phyCORE OMAP44xx allows to choose which signal...

Page 133: ... 3 14 GND Ground 15 CAM 2_DD4 I VCC_CAM 2 Camera 2 data input 4 16 CAM 2_DD5 I VCC_CAM 2 Camera_2 data input 5 17 GND Ground 18 CAM 2_DD6 I VCC_CAM 2 Camera_2 data input 6 19 CAM 2_DD7 I VCC_CAM 2 Camera_2 data input 7 20 GND Ground 21 CAM 2_DD8 I VCC_CAM 2 Camera_2 data input 8 22 CAM 2_DD9 I VCC_CAM 2 Camera 2 data input 9 23 GND Ground 24 CAM 2_HS I VCC_CAM 2 Camera_2 horizontal sync 25 CAM 2_V...

Page 134: ...als to GND 2 1 3 9 3 Camera Auxiliary Connector X2 The camera auxiliary connector X2 can be used to configure camera control signals CAM 1_CTRL1 and CAM 1_CTRL2 They are available at expansion connector X5 to support implementation of a custom camera interface using the primary camera interface CSI2 A CSI21 of the OMAP44xx Removable jumpers can be used to connect CAM 1_CTRL1 and CAM 1_CTRL2 to GND...

Page 135: ...rved for future use 20 CAM 1_DD4 I VCC_CAM 1 Reserved for future use 21 CAM 1_DD3 I VCC_CAM 1 Reserved for future use 22 CAM 1_DD2 I VCC_CAM 1 Reserved for future use 23 CAM 1_DD1 I VCC_CAM 1 Reserved for future use 24 CAM 1_DD0 I VCC_CAM 1 Reserved for future use 25 GND Ground 26 CAM 1_PCLK I VCC_CAM 1 Reserved for future use 27 GND Ground 28 CAM 1_MCLK O VCC_CAM 1 Reserved for future use 29 GND ...

Page 136: ...HYTEC Messtechnik GmbH 2012 L 760e_1 2 1 3 10 Audio Connectivity X5 X14 X15 X17 Figure 33 Components supporting the Audio Interface at connectors X5 X14 X15 and X17 top view Figure 34 Components supporting the Audio Interface at connectors X5 X14 X15 and X17 bottom view ...

Page 137: ...ne Inputs MIC1 MIC2 X17 Line Input Line_INL Line_INR Please refer to the audio codec s reference manual for additional information regarding the special interface specification Jumper J13 allows flexible control over the audio codec s master clock source MCLK In the default position 2 3 the codec is clocked from the module s X_FREF_CLK4_REQ clock signal The audio codec s master clock can range fro...

Page 138: ...rt II PCM 959 phyCORE OMAP44xx Carrier Board phyCORE OMAP44xx 126 PHYTEC Messtechnik GmbH 2012 L 760e_1 2 1 3 11 I2C Connectivity Figure 35 I2C Connectivity top view Figure 36 I2C Connectivity bottom view ...

Page 139: ... the default address Connector Location SL Connectors providing I C interface I2C1 Expansion connector X5 pin 2C I2C1_SDA_3V3 pin 1C I2C1_SCL_3V3 3 3 V Connectors providing I C interface I2C3 Camera_1 interface X201 1 To use the Camera_1 I2 C interface JP6 must be closed to have VCC_CAM_1 available pin 29 CAM 1_SDA pin 28 CAM 1_SCL VCC_CAM 1 Camera_1 interface X21 pin 9 CAM 1_SDA pin 10 CAM 1_SCL ...

Page 140: ... Address standard 7 MSB Maximum Speed I2C3 Camera Boards with phyCAM P interface connected to X4 I2C interface of the image sensor all camera boards Depends on the camera board VM 00x connect ed to this interface Please refer to the corre sponding phyCAM P phyCAM S manual L 748 I2C interface of the bus expander only cameras which allow for dynamic switching between 8 10 bit interface 0x41 Equal to...

Page 141: ... X18 and X19 as well as at the display data connector X12 and the expansion connector X5 Table 61 shows the assignment of the SPI chip select signals to the different connectors The second SPI interface is derived from the Multichannel Audio Serial McASP interface pins of the phyCORE OMAP44xx as these pins embody the signals of the second SPI module SPI2 as alternative function This inter face pro...

Page 142: ...arrier Board already This also applies to the three dedicated GPIOs of the phyCORE OMAP44xx Special functions have been assigned to these GPIOs in order to demonstrate their use see also Table 42 Signals not used extend from the phyCORE Connector X22 directly to the expansion connector X5 The following table lists all signals available as GPIOs In order to use the GPIOs the software must be change...

Page 143: ...eren tial data lane negative input 1 X_CSI21_DX2 X5C22 I CSI GPI 71 or CSI2 A CSI21 differen tial data lane positive input 2 X_CSI21_DY2 X5C23 I 1 8 V CSI GPI 72 or CSI2 A CSI21 differen tial data lane negative input 2 X_UART1_TX X5C35 I O 1 8 V GPIO 129 or UART1 transmit X_UART1_RX X5C36 I O 1 8 V GPIO 128 or UART1 receive X_SDMMC1_DAT4 X5D1 I O VCC_MMC1 GPIO 106 or SD MMC1 Data 4 X_SDMMC1_DAT5 X...

Page 144: ...ed to the phyCORE s I2C4 bus The I2C address is 0x62 The user LEDs are free programmable for example a Heartbeat Connect detection of SD MMC card or other things The LEDs are in different colors on the carrier board In cases of need it can assembled with other color LEDs LED title LED color description D41 red User LED 1 LED driver 0 of the PCA9533 D39 yellow User LED 2 LED driver 1 of the PCA9533...

Page 145: ... the functionality without expanding the physical dimensions Mounting wholes can be used to screw the additional PCBs to the phyCORE OMAP44xx Carrier Board When referencing pin numbers note that pin 1 is located at the angled corner Pins towards the labeling X18 or X19 are odd numbered The extension connectors share the SPI interface of the phyCORE OMAP44xx with the display data connector X12 but ...

Page 146: ... 3 V Hardware Introspection Interf For internal use only 10 GND Ground 11 SPI1_CS0_3V3 SPI1_CS1_3V3 O 3 3 V X19 SPI chip select extension port 0 X18 SPI chip select extension port 1 12 SPI1_MOSI_V3 O 3 3 V SPI master output slave input 13 SPI1_CLK_3V3 O 3 3 V SPI clock output 14 SPI1_MISO_3V3 I 3 3 V SPI master input slave output 15 SPI1_RDY_3V3 I O 3 3 V SPI data ready input master mode only 16 S...

Page 147: ...TEC Messtechnik GmbH 2012 135 2 1 3 16 Secure Digital Memory MultiMedia Card Slots X10 X11 Figure 41 Components supporting the SD MM Card interfaces at connector X10 and X11 top view Figure 42 Components supporting the SD MM Card interfaces at connector X10 and X11 bottom view ...

Page 148: ...level of the supply voltage VCC_SDMMC5 The default level is 3 3 V VCC_3V3 J12 at position 1 2 Closing jumper J12 at 2 3 results in a supply voltage of 1 8 V VCC_1V8 Removing the level shifter and mounting RN1 R157 and R155 connects the SD MMC Card interface SDMMC5 of the phyCORE OMAP44xx directly to SD MMC card slot 2 X10 SD MMC card slot 1 X11 connects to the OMAP44xx s SD MMC Card interface SDMM...

Page 149: ... There are always two switches connected to one X BOOT input One switch pulls X_BOOT x to LOW and the second one to HIGH With both switches turned OFF the default value predefined by the resistor network on the phyCORE OMAP44xx is valid at the corresponding sys_boot configuration pin of the OMAP44xx The following table shows the possible settings of the first two switches S1_1 and S1_2 as an examp...

Page 150: ...to the configuration circuitry pull up or pull down resistors on the phyCORE OMAP44xx S1_1 connecting to GND On Off Off S1_2 connecting to VCC_1V8 Off On Off Table 66 Possible Configurations of the DIP Switches1 1 Default settings are in bold blue text phyCORE Configuration Pin OMAP44xx Configuration Pin S1_1 S1_2 X_BOOT0 X1C57 sys_boot 0 S1_3 S1_4 X_BOOT1 X1D57 sys_boot 1 S2_1 S2_2 X_BOOT2 X1C58 ...

Page 151: ...stem reset signal Pressing this button will toggle the X_nRESET_PWRON signal LOW causing a reset of the phyCORE OMAP44xx and the peripheral devices on the carrier board If the Lithium Ion Battery BAT1 is assembled and VCC_3V3 falls below 2 9 V then the reset device U23 connects the Lithium Ion Battery to the backup battery input VBAT of the phyCORE OMAP44xx This way the RTC and some critical regis...

Page 152: ... of the phyCORE OMAP44xx is accessible at connector X1 on the carrier board This interface is compliant with JTAG specification IEEE 1149 1 or IEEE 1149 7 No jumper settings are necessary for using the JTAG port The following table describes the signal configuration at X1 When referencing contact numbers note that pin 1 is located at the angled corner Pins towards the labeling JTAG are even number...

Page 153: ...Test Reset 4 6 8 10 12 14 18 20 GND Ground 5 X_JTAG_TDI I 1 8 V JTAG Chain Test Data input 7 X_JTAG_TMS I O 1 8 V JTAG Chain Test Mode Select signal 9 X_JTAG_TCK I 1 8 V JTAG Chain Test Clock signal 11 X_JTAG_RTCK O 1 8 V JTAG Chain Return Test Clock signal 13 X_JTAG_TDO O 1 8 V JTAG Chain Test Data Output 15 X_nRESET_WARM I 1 8 V System Reset 17 X_DPM_EMU0 I O 1 8 V Debug Request 19 X_DPM_EMU1 I ...

Page 154: ...X19 are even numbered while contacts towards the labeling Keypad are odd numbered The keypad connector supports multiconfiguration keypads with up to 6 rows x 6 columns up to 36 keys The reference voltage VCC_1V8_IO and the supply voltage VCC_3V3 are also available at the keypad connector The following table describes the signal mapping at X21 Location Signal I O SL Description 1 VCC_1V8_IO O VCC_...

Page 155: ... 14 X_KPD_ROW5_CSI21_DY4 I 1 8 V CSI Keyboardrow5 CSI2 A CSI21 differential data lane negative input 4 see note below 15 16 GND Ground Note Contacts 10 to 13 of the keypad connector provide either signals of the keyboard interface or camera lanes 3 and 4 of the primary camera interface The resistor array JN1 on the phyCORE OMAP44xx allows to choose whichsignalsarebroughtoutatthesepins Thedefaultse...

Page 156: ...oard phyCORE OMAP44xx 144 PHYTEC Messtechnik GmbH 2012 L 760e_1 2 1 3 21 Expansion Connector X5 Figure 47 Expansion Connector X5 Unused signals or functions of the phyCORE OMAP44xx or the carrier board are partial on the expansion connector X5 ...

Page 157: ...ATA17 X5A11 O 1 8 V parallel display data 17 X_DISPC_DATA18 X5A12 O 1 8 V parallel display data 18 X_DISPC_DATA19 X5A13 O 1 8 V parallel display data 19 X_DISPC_DATA20 X5A14 O 1 8 V parallel display data 20 X_DISPC_DATA21 X5A15 O 1 8 V parallel display data 21 X_DISPC_DATA22 X5A16 O 1 8 V parallel display data 22 X_DISPC_DATA23 X5A17 O 1 8 V parallel display data 23 X_DISPC_DATA8 X5B1 O 1 8 V para...

Page 158: ...B2 Interface Data 1 usbb2_ulpi_dat1 X_DISPC_DATA20 X5A14 I O 1 8 V USBB2 Interface Data 0 usbb2_ulpi_dat0 X_DISPC_DATA21 X5A15 I 1 8 V USBB2 Interface Next usbb2_ulpi_nxt X_DISPC_DATA22 X5A16 I 1 8 V USBB2 Interface Direction usbb2_ulpi_dir X_DISPC_DATA23 X5A17 O 1 8 V USBB2 Interface Stop usbb2_ulpi_stp X_DISPC_DATA11 X5B4 I O 1 8 V USBB2 Interface Data 7 usbb2_ulpi_dat7 X_DISPC_DATA12 X5B5 I O 1...

Page 159: ... X5C8 I O 3 3 V I2C4 data signal CAM 1_SCL X5C10 I O VCC_CAM 1 Camera 1 I2 C clock signal1 1 To use the Camera_1 I2 C interface JP6 must be closed to have VCC_CAM 1 available CAM 1_SDA X5C11 I O VCC_CAM 1 Camera 1 I2 C data signal1 CAM 2_SCL X5D6 I O VCC_CAM 2 Camera 2 I2 C clock signal2 2 To use the Camera_2 I2 C interface JP1 must be closed to have VCC_CAM 2 available CAM 2_SDA X5D7 I O VCC_CAM ...

Page 160: ...positive input 4 X_KPD_ROW5_CSI21_DY4 X5C27 I 1 8 V CSI Keyboard row 5 CSI2 A CSI21 differential data lane negative input 4 Note The function of camera control signals CAM 1_CTRL1 and CAM 1_CTRL2 depends on the camera board used Connector X2 allows to connect them either to GND or VCC CAM 1 or any other signal needed Please refer to the hardware manual delivered with your camera board for precise ...

Page 161: ... second SPI interface provides only one chip select signal CS0 2 1 3 21 7 UART1 Signal Mapping The expansion connector X5 provides the UART1 Interface of the phyCORE OMAP44xx Signal Extension Bus I O SL Description X_McASP_AMUTEIN_GPIO_117 X5D15 I 1 8 V Mute in from external at 1 8 V McSPI2_CLK_3V3 X5D16 I O 3 3 V SPI2 Interface Clock McASP transmit high frequency master clock McASP_AHCLKX McSPI2_...

Page 162: ...on X_PMIC_SYSEN X5C38 O 1 8 V Sysen output for switching an extern power source X_PMIC_EXTCHRG_ENZ X5C39 O 1 8 V Control output to extern Loading IC X_PMIC_VAC X5C40 I extern VAC charger input X_PMIC_CHRG_EXTCHRG_STATZ X5C41 I 1 8 V Status input from extern Loading IC X_PMIC_CLK32KAUDIO X5D37 O 1 8 V 32K Clock Table 77 PMIC Signal Mapping Signal Pin I O SL Description X_USBC1_ICUSB_DP X5D12 I O US...

Page 163: ...5D47 X5D48 O 1 8 V 1 8 V reference domain VCC_1V2 X5D33 O 1 2 V 1 2 V reference domain Table 81 Power Signal Mapping Signal Pin I O SL Description X_CSI21_DX0 X5C18 I CSI GPI 67 or CSI2 A CSI21 differential clock positive input X_CSI21_DY0 X5C19 I CSI GPI 68 or CSI2 A CSI21 differential clock negative input X_CSI21_DX1 X5C20 I CSI GPI 69 or CSI2 A CSI21 differential data lane positive input 1 X_CS...

Page 164: ... USB GPIO 99 or USBC1 data minus X_USBB1_OC_GPIO_ 120 X5D35 I 1 8 V GPIO 120 or USB Host overcurrent signal input Note The function of camera control signals CAM 1_CTRL1 and CAM 1_CTRL2 depends on the camera board used Connector X2 allows to connect them either to GND or VCC CAM 1 or any other signal needed Please refer to the hardware manual delivered with your camera board for precise informatio...

Page 165: ...60e_1 PHYTEC Messtechnik GmbH 2012 153 2 1 3 22 Carrier Board Physical Dimensions Figure 48 Carrier board physical dimensions Please contact us if a more detailed dimensioned drawing is needed to integrate the phyCORE OMAP44xx Carrier Board into a customer application ...

Page 166: ...Part II PCM 959 phyCORE OMAP44xx Carrier Board phyCORE OMAP44xx 154 PHYTEC Messtechnik GmbH 2012 L 760e_1 ...

Page 167: ...mbers Changes in this manual 01 07 2011 Manual L 760e_0 First draft Preliminary documentation Describes the phyCORE OMAP44xx with phyCORE OMAP44xx Carrier Board 20 03 2012 Manual L 760e_1 Final documentation Describes the phyCORE OMAP44xx with phyCORE OMAP44xx Carrier Board PCB Numbers 1347 1 SOM and 1348 2 CB ...

Page 168: ...Revision History phyCORE OMAP44xx 172 PHYTEC Messtechnik GmbH 2012 L 760e_1 ...

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