Phytec phyCORE-OMAP44 Series, Hardware Manual

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Part I: PCM-049/phyCORE-OMAP44xx System on Module phyCORE-OMAP44xx
22 ©
PHYTEC Messtechnik GmbH
2012
L-760e_1
16B X_CSI21_DY2 I CSI CSI2-A (CSI21) differential data
lane negative input 2
17B X_I2C4_SCL O VCC_1V8_IO I
2
C4 clock (open drain)
18B VCC_MMC1 O 1.8 V - 3.3 V SDMMC1 reference voltage
19B GND - - Ground 0V
20B X_SDMMC5_CMD I/O 1.8 V / VCC_1V8_IO SDMMC5 command
21B X_SDMMC5_CLK O VCC_1V8_IO SDMMC5 clock
22B X_SDMMC5_DAT0 I/O 1.8 V / VCC_1V8_IO SDMMC5 data bit 0
23B X_SDMMC5_DAT1 I/O 1.8 V / VCC_1V8_IO SDMMC5 data bit 1
24B GND - - Ground 0V
25B X_SDMMC5_DAT2 I/O 1.8 V / VCC_1V8_IO SDMMC5 data bit 2
26B X_SDMMC5_DAT3 I/O 1.8 V / VCC_1V8_IO SDMMC5 data bit 3
27B X_PMIC_MMC1_CD I 1.8 V SDMMC1 card insertion and
extraction detection
28B X_McBSP3_CLKX I/O 1.8 V / VCC_1V8_IO ABE McBSP3 combined serial clock
29B GND - - Ground 0V
30B VCC_1V8_IO O - 1.8 V IO reference voltage
31B X_SPI1_CS1 O VCC_1V8_IO McSPI1 chip select 1
32B X_SPI1_CS2 O VCC_1V8_IO McSPI1 chip select 2
33B X_SPI1_MOSI I/O 1.8 V / VCC_1V8_IO McSPI1 master output / slave
input
34B X_SPI1_CLK I/O 1.8 V / VCC_1V8_IO McSPI1 clock master output /
slave input
35B GND - - Ground 0V
36B X_ABE_CLKS I 1.8 V ABE clock input
37B X_McASP_AHCLKX O VCC_1V8_IO ABE McASP high frequency clock
output
38B McASP_AMUTE O VCC_1V8_IO ABE McASP auto mute output
39B X_GPIO_114 I/O 1.8 V / VCC_1V8_IO GPIO 114
40B GND - - Ground 0V
41B X_McBSP3_FSX I/O 1.8 V / VCC_1V8_IO ABE McBSP3 combined frame
synchronization
42B X_McBSP3_DR I 1.8 V ABE McBSP3 received serial data
43B X_DISPC_DATA23 O VCC_1V8_IO DISPC data bit 23
Pin Row X1B
Pin # Signal I/O SL Description
Table 3:
Pin-out of the phyCORE-Connector X1, Row B