Part I: PCM-049/phyCORE-OMAP44xx System on Module
phyCORE-OMAP44xx
36
©
PHYTEC Messtechnik GmbH
2012
L-760e_1
1.4.3 Power Management IC (U5)
The phyCORE-OMAP44xx provides an on-board Power Management IC (PMIC) TWL6030 at position U5 to source
the different voltages required by the processor and on-board components.
depiction of the powering scheme.
The TWL6030 supports many functions like on-chip RTC and different power management functionalities.
It is connected to the OMAP44xx via the I2C1 bus and the OMAP44xx smart reflex bus. The I2C1 addresses of the
TWL6030 are 0x48, 0x49 and 0x4A (7 MSB). The smart reflex address is 0x12 (7MSB).
Please refer to the Texas Instruments TWL6030 datasheet for further information.
1.4.3.1 Power domains
The PMIC has two input voltage rails as can be seen in
VCC_3V3 and VBAT. VCC_3V3 is supplied from the
primary voltage input pins VCC_3V3_IN of the phyCORE-OMAP44xx, whereas VBAT is supplied from the
secondary voltage input pin X1C7. The following list summarizes the relation between the different voltage rails
and the devices on the phyCORE-OMAP44xx:
External voltages: VCC_3V3_IN and VBAT (optional)
•
VCC_3V3_IN: Voltage Regulator, 1-Wire Levelshifter, 1-Wire EEPROM (via current sense amplifier at U9)
•
VBAT: Voltage Regulator
Internally generated voltages: VCC_CORE1 (0.93 V-1.1 V), VCC_CORE2 (0.93 V-1.1 V), VCC_CORE3
(0.93 V-1.1 V), VCC_1V8_IO (1.8 V), VCC_MEM (1.2 V), VCC_V1V29 (1.2 V), VCC_2V1 (2.1 V), VCC_CXIO (1.8 V),
VCC_DAC (1.8 V), VCC_MMC1 (3 V/1.8 V), VCC_3V3_S (3.3 V), VCC_PP (3.3 V), VCC_USB_3V3 (3.3 V)
•
VCC_CORE1 (0.93 V-1.1 V) OMAP44xx mpu (VDD_MPU)
•
VCC_CORE2 (0.93 V-1.1 V) OMAP44xx iva audio (VDD_IVA_AUDIO)
•
VCC_CORE3 (0.93 V-1.1 V) OMAP44xx core (VDD_CORE), dll (VDDA_DLL)
•
VCC_PP (3.3 V) OMAP44xx eFuse prgr. module (VPP_CUST)
•
VCC_USB_3V3 (3.3 V) OMAP44xx USB OTG 0 (VDDA_USBA0OTG_3P3V)
•
VCC_1V8_IO (1.8 V) OMAP44xx IO, OMAP44xx LPDDR2 pop memory (POP_VDD1_LPDDR), USB PHY IO,
Ethernet controller IO, EEPROM, NAND-Flash, MMC2, logic of the RS-232 transceiver,
IO reference voltage at phyCORE-Connector X1B30, signal level of I
2
C, SPI and JTAG
interfaces
•
VCC_MEM (1.2 V) OMAP44xx LPDDR2 pop memory (POP_VDD2_LPDDR)
•
VCC_V1V29 (1.2 V) OMAP44xx LPDDR2 (VDDQ_LPDDR2, VDDCA_LPDDR2) and LDO (VDDA_LDO)
•
VCC_2V1 (2.1 V) PMIC, used to generate VCC_CXIO and VCC_DAC via LDOs
•
VCC_CXIO (1.8 V) OMAP44xx DSI (VDDA_DSI), CSI (VDDA_CSI), OTG (VDDA_USBA0OTG_1P8V), and DPLL
(VDDA_DPLL)
•
VCC_DAC (1.8 V) OMAP44xx HDMI (VDDA_HDMI)
•
VCC_MMC1 (3 V/1.8 V) OMAP44xx MMC (VDDS_SDMMC1) and MMC1 reference voltage at phyCORE-Connector
X1B18 (switchable between 3 V and 1.8 V via PMIC register, default 3 V)
•
VCC_3V3_S (3.3 V) RS-232 Transceiver, USB PHY, Ethernet controller, User LEDs, 3V3_S reference voltage
at phyCORE-Connector X1D23 (connected to main supply VCC_3V3 through FET Q3,
switchable via PMIC REGEN1 output)
