Part II: PCM-959/phyCORE-OMAP44xx Carrier Board
phyCORE-OMAP44xx
146
©
PHYTEC Messtechnik GmbH
2012
L-760e_1
2.1.3.21.2 USBB2 Signal Mapping
If the parallel display interface of the OMAP44xx is not needed to drive a display some of the pins can be
combined to design an additional USB interface using port 2 of the OMAP44xx's high speed USB host
subsystem. The HS USB host subsystem supports the 12-pin/8-bit data SDR version of the ULPI mode and allows
connection to either an USB transceiver (in ULPI mode), or an USB controller (in ULPI TLL interface mode)
(refer to the OMAP44xx Reference Manual). The following table shows the location of the ULPI interface signals
with reference to the signal names at the phyCORE-Connector.
Signal
Pin #
I/O
SL
Description
X_DISPC_DATA18
X5A12
I/O
1.8 V
USBB2 Interface Data 2
(usbb2_ulpi_dat2)
X_DISPC_DATA19
X5A13
I/O
1.8 V
USBB2 Interface Data 1
(usbb2_ulpi_dat1)
X_DISPC_DATA20
X5A14
I/O
1.8 V
USBB2 Interface Data 0
(usbb2_ulpi_dat0)
X_DISPC_DATA21
X5A15
I
1.8 V
USBB2 Interface Next
(usbb2_ulpi_nxt)
X_DISPC_DATA22
X5A16
I
1.8 V
USBB2 Interface Direction
(usbb2_ulpi_dir)
X_DISPC_DATA23
X5A17
O
1.8 V
USBB2 Interface Stop
(usbb2_ulpi_stp)
X_DISPC_DATA11
X5B4
I/O
1.8 V
USBB2 Interface Data 7
(usbb2_ulpi_dat7)
X_DISPC_DATA12
X5B5
I/O
1.8 V
USBB2 Interface Data 6
(usbb2_ulpi_dat6)
X_DISPC_DATA13
X5B6
I/O
1.8 V
USBB2 Interface Data 5
(usbb2_ulpi_dat5)
X_DISPC_DATA14
X5B7
I/O
1.8 V
USBB2 Interface Data 4
(usbb2_ulpi_dat5)
X_DISPC_DATA15
X5B8
I/O
1.8 V
USBB2 Interface Data 3
(usbb2_ulpi_dat3)
X_DMTIMER9_PWM_EVT
X5B15
I
1.8 V
USBB2 Interface Clock
1
(usbb2_ulpi_clk)
1.
Jumper J6 on the phyCORE-OMAP44xx must be configured at 2+3 to have this signal available (see
Table 71:
USBB2 Signal Mapping
Note:
Jumper JP14 should be closed at position 2+3 in order to shut down the FlatLink™ transmitter which also
connects to these signals. This allows to avoid signal conflicts and to reduce disturbances.
