Phytec phyCORE-OMAP44 Series, Hardware Manual

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Part I: PCM-049/phyCORE-OMAP44xx System on Module phyCORE-OMAP44xx
54 ©
PHYTEC Messtechnik GmbH
2012
L-760e_1
1.8.6 I
2
C Interface
The Inter-Integrated Circuit (I
2
C) interface is a two-wire, bidirectional serial bus that provides a simple and
efficient method for data exchange among devices. The OMAP44xx contains 4 identical and independent I
2
C
modules. The interface of the first, third and fourth module are available on the phyCORE-Connector. The first
module connects also to the on-board EEPROM (refer to
Section 1.6.3 ) and to the PMIC TWL6030 (refer to
Section 1.4.3 ). The following table lists the I
2
C ports on the phyCORE-Connector.
To avoid any conflicts when connecting external I
2
C devices to the first I
2
C module of the OMAP44xx the
addresses of the on-board I
2
C devices must be considered. Table 23 lists the addresses already in use.
The addresses of the EEPROM can be configured by jumpers. The table shows only the default addresses.
Please refer to
Section 1.6.3.1 for alternative address settings.
Pin # Signal I/O SL Description
X1C53 X_I2C1_SCL O VCC_1V8_IO I2C1 clock (open drain)
X1C54 X_I2C1_SDA I/O 1.8 V / VCC_1V8_IO I2C1 data (open drain)
X1D51 X_I2C3_SCL O VCC_1V8_IO I2C3 clock (open drain)
X1D52 X_I2C3_SDA I/O 1.8 V / VCC_1V8_IO I2C3 data (open drain)
X1A18 X_I2C4_SDA I/O 1.8 V / VCC_1V8_IO I2C4 data (open drain)
X1B17 X_I2C4_SCL O VCC_1V8_IO I2C4 clock (open drain)
Table 22:
I
2
C Interface Signal Location
I
2
C Interface Connected Devices I
2
C Address
(standard)(7 MSB)
Maximum Speed
I2C1 EEPROM 0x50 400 kHz
I2C1 PMIC 0x48, 0x49, 0x4A 400 kHz
Table 23: I
2
C Addresses in Use