Phytec phyCORE-i.MX35, Hardware Manual

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phyCORE-i.MX35
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PHYTEC Messtechnik GmbH 2010 L-734e_1
7.2 DDR2-SDRAM (U6-U7)
The phyCORE-i.MX35 has one bank of DDR2-SDRAMs on the i.MX35x module.
The RAM bank is comprised of two 16-bit wide DDR2-SDRAM chips, configured for 32-bit access,
and operating at 133MHz. In lower density configurations, U6 and U7 populate the module and are
accessed via SDRAM memory bank 0 using chip select signal /CSD0 starting at 0x8000 0000.
Actually there is no RAM bank 1 for the i.MX35x. So the /CSD1 chip select line is freed and can be
used as /CS3.
Typically the DDR2-SDRAM initialization is performed by a boot loader or operating system following
a power-on reset and must not be changed at a later point by any application code. When writing
custom code independent of an operating system or boot loader, SDRAM must be initialized by
accessing the appropriate SDRAM configuration registers on the i.MX35x controller.
Refer to the
i.MX35 User Manual for accessing and configuring these registers.