Phytec phyCORE-i.MX35, Hardware Manual

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Pin Description

PHYTEC Messtechnik GmbH 2010 L-734e_1
9
Note:
SL is short for Signal Level (V) and is the applicable logic level to interface a given pin.
Table 1: Pin-out of the phyCORE-Connector X1
P
IN
R
OW
X1A
P
IN
# S
IGNAL
I/O SL D
ESCRIPTION
1A VDD_3V3 - VDD_3V3 LCD reference voltage (3.3 V)
2A GND - 0 Ground 0 V
3A not connected - - Pin left unconnected
4A not connected - - Pin left unconnected
5A X_LCD_VSYNC I/O VDD_3V3 Display vertical synchronization pulse
6A not connected - - Pin left unconnected
7A GND - 0 Ground 0 V
8A X_LCD_REV O VDD_3V3 REV signal for display
9A X_LCD_SPL O VDD_3V3 SPL/SPR signal for display
10A X_LCD_DRDY O VDD_3V3 Data enable signal for display
11A not connected - - Pin left unconnected
12A GND - 0 Ground 0 V
13A X_LCD_LD0 I/O VDD_3V3 Input/Output data 0 to display
14A X_LCD_LD2 I/O VDD_3V3 Input/Output data 2 to display
15A X_LCD_LD3 I/O VDD_3V3 Input/Output data 3 to display
16A X_LCD_LD5 I/O VDD_3V3 Input/Output data 5 to display
17A GND - 0 Ground 0 V
18A X_LCD_LD8 I/O VDD_3V3 Input/Output data 8 to display
19A X_LCD_LD10 I/O VDD_3V3 Input/Output data 10 to display
20A X_LCD_LD11 I/O VDD_3V3 Input/Output data 11 to display
21A X_LCD_LD13 I/O VDD_3V3 Input/Output data 13 to display
22A GND - 0 Ground 0 V
23A X_LCD_LD17 I/O VDD_3V3 Input/Output data 17 to display
24A X_LCD_LD18 I/O VDD_3V3 Input/Output data 18 to display
25A X_LCD_LD19 I/O VDD_3V3 Input/Output data 19 to display
26A X_LCD_LD21 I/O VDD_3V3 Input/Output data 21 to display
27A GND - 0 Ground 0 V
28A #CS0_3V3 O VDD_3V3 Chip Select 0 output
29A #CS1_3V3 O VDD_3V3 Chip Select 1 output
30A #CS4_3V3 O VDD_3V3 Chip Select 4 output
31A EB1_3V3 O VDD_3V3 Active low external enable byte signal that
controls
D[7:0]
32A GND - 0 Ground 0 V