Phytec phyCORE-i.MX35 Hardware Manual Download Page 101

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The phyCORE-i.MX on the Development Board



PHYTEC Messtechnik GmbH 2010 L-734e_1

Table 31: Camera Interface Jumper Settings for i.MX35 Module

UMPER

ETTING

ESCRIPTION

JP3

closed

open

Outputs of level shifter U12 are enabled, CSI is active

Outputs of U12 are disabled or GPIO x_CSI_ENABLE can be used to
control U12

JP16

1 + 2

2 + 3

Jumper settings to chance camera sensor specific I²C address.

For more

information refer to the manual of the used camera sensor.

JP15

1 + 2

2 + 3

Use of Camera Connector X7 with VCC_CAM supply (3.3 V)

Use of Camera Connector X8 with external VCC_CAM_EXT supply

Summary of Contents for phyCORE-i.MX35

Page 1: ...A product of a PHYTEC Technology Holding company phyCORE i MX35 HARDWARE MANUAL EDITION JUNE 2010...

Page 2: ...C Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserv...

Page 3: ...Power Up Mode 28 6 1 2 Boot Mode Select 29 7 System Memory 30 7 1 Memory Model 31 7 2 DDR2 SDRAM U6 U7 32 7 3 NOR Flash U9 33 7 4 NAND Flash Memory U10 34 7 5 I C EEPROM U2 35 7 5 1 Setting the EEPRO...

Page 4: ...ot Select Switch 70 15 2 6 phyMAP i MX35 Mapper Physical Dimensions 72 15 3 Cooperation of phyCORE i MX35 and phyCORE i MX Carrier Board 73 15 3 1 Power Supply 74 15 3 2 CAN Interface 78 15 3 3 Push B...

Page 5: ...Board Connection Using the phyMAP i MX35 53 Figure 12 phyMAP i MX35 Top View 54 Figure 13 phyMAP i MX35 Bottom View 55 Figure 14 Jumper Location on PMA 005 56 Figure 15 PMA 005 USB Host Interface 66...

Page 6: ...10 L 734e_1 Figure 27 phyCORE i MX Carrier Board Camera Interface 92 Figure 28 phyCORE iMX Carrier Board JTAG Interface 95 Figure 29 phyCORE i MX35 Component Placement Top View 102 Figure 30 phyCORE i...

Page 7: ...4 UART2 Signal Routing 39 Table 12 Fast Ethernet Controller Memory Map 41 Table 13 CAN Controller Memory Map 42 Table 14 JTAG Connector X2 Signal Assignment 46 Table 15 Jumper Settings of PMA 005 58 T...

Page 8: ...29 Audio Touchscreen Interface Jumper Settings for i MX35 Module 87 Table 30 UBS Host Interface Jumper Settings for i MX35 Module 89 Table 31 Camera Interface Jumper Settings for i MX35 Module 93 Tabl...

Page 9: ...e operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Con...

Page 10: ...ng EMI and EMC guidelines using phyCORE boards even in high noise environments phyCORE boards achieve their small size through modern SMD technology and multi layer design In accordance with the compl...

Page 11: ...yte up to 64MByte Intel Strata NOR Flash 1 GByte up to 32 GByte on board NAND Flash1 128 MByte up to 256 MByte DDR2 SDRAM on board RS 232 transceiver supporting one UART at data rates of up to 460kbps...

Page 12: ...phyCORE i MX35 4 PHYTEC Messtechnik GmbH 2010 L 734e_1 1 2 Block Diagram Figure 1 Block Diagram of the phyCORE i MX35...

Page 13: ...0 R84 R69 XT2 L15 R78 C177 C97 U14 U1 U7 C171 R23 C84 C182 C13 L14 C89 TP9 C74 C113 U13 C33 XT3 C123 C106 R30 J10 C190 C102 L16 C94 R21 R40 C175 C25 C46 U16 R73 C112 C88 J1 R80 C77 R52 J11 TP5 R77 R28...

Page 14: ...U12 L6 C30 C35 C8 C59 C137 C118 R16 L1 C167 TP15 R18 C195 U3 C139 C5 R2 R11 C119 C56 R7 C170 C19 L2 R100 R96 C23 C151 J2 C21 J3 R42 U20 C2 R10 C16 R3 C26 C64 C37 C148 C71 R98 R82 R33 C100 C65 C22 C163...

Page 15: ...he pin connector rows progresses alphabetically from left to right refer to Figure 4 The numbered matrix can be aligned with the phyCORE i MX35 viewed from above phyCORE connector pointing down or wit...

Page 16: ...1 also provides the appropriate signal level interface voltages listed in the SL Signal Level column The Freescale i MX35 is a multi voltage operated microcontroller and as such special attention shou...

Page 17: ...data 0 to display 14A X_LCD_LD2 I O VDD_3V3 Input Output data 2 to display 15A X_LCD_LD3 I O VDD_3V3 Input Output data 3 to display 16A X_LCD_LD5 I O VDD_3V3 Input Output data 5 to display 17A GND 0...

Page 18: ...VDD_3V3 Address Line A21 50A A23_3V3 O VDD_3V3 Address Line A23 51A D0 I O VDD_3V3 Data_Bus D0 52A GND 0 Ground 0 V 53A D2 I O VDD_3V3 Data_Bus D2 54A D3 I O VDD_3V3 Data_Bus D3 55A D5 I O VDD_3V3 Da...

Page 19: ...Camera Sensor D14 84A X_CSI_MCLK O VDD_3V3 Camera Sensor Master Clock 85A X_CSI_VSYNC I VDD_3V3 Camera Sensor vertical sync 86A X_CSI_PIXCLK I VDD_3V3 Camera Sensor pixel clock 87A GND 0 Ground 0 V 88...

Page 20: ...lay 17B X_LCD_LD7 I O VDD_3V3 Input Output data 7 to display 18B X_LCD_LD9 I O VDD_3V3 Input Output data 9 to display 19B GND 0 Ground 0 V 20B X_LCD_LD12 I O VDD_3V3 Input Output data 12 to display 21...

Page 21: ...3V3 Data_Bus D12 59B GND 0 Ground 0 V 60B D14 I O VDD_3V3 Data_Bus D14 61B D15 I O VDD_3V3 Data_Bus D15 62B X_FL_WP I VDD_3V3 NOR Flash write protect signal 63B not connected Pin left unconnected 64B...

Page 22: ...1 O VDD_3V3 Fast Ethernet Transmit Data 1 88B X_FEC_TDATA2 O VDD_3V3 Fast Ethernet Transmit Data 2 89B GND 0 Ground 0 V 90B X_KEY_ROW0 I O VDD_3V3 Keypad Port Row 0 91B X_KEY_ROW1 I O VDD_3V3 Keypad P...

Page 23: ...onnected Pin left unconnected 17C GND 0 Ground 0 V 18C not connected Pin left unconnected 19C not connected Pin left unconnected 20C not connected Pin left unconnected 21C not connected Pin left uncon...

Page 24: ...USBPHY1_DP I O VDD_3V3 USB1 transceiver cable interface D 56C X_USBPHY1_UID I O VDD_3V3 USB1 on the go transceiver cable ID resistor connection 57C GND 0 Ground 0 V 58C not connected Pin left unconnec...

Page 25: ...84C X_I2C3_SDA I O VDD_3V3 I C 3 Serial Data 85C X_I2C1_DAT I O VDD_3V3 I C 1 Serial Data 86C X_CSPI1_SCLK I O VDD_3V3 SPI 1 clock 87C GND 0 Ground 0 V 88C X_CSPI1_SS0 I O VDD_3V3 SPI 1 Chip select 0...

Page 26: ...3 V power switch 16D X_EN_VDD_1V8 I VIN Enable for 1 8 V power switch 17D X_EN_VDD_1V375 I VIN Enable for 1 375 V power switch 18D X_EN_LDO1_2 I VIN Enable for power supply LDO 3 3 V 1 8 V 19D GND 0 G...

Page 27: ...2D X_SD2_DATA2 I O VDD_3V3 SD MMC 2 Data2 line or Read wait in 4 bit mode Read wait in 1 bit mode 53D X_SD2_DATA3 I O VDD_3V3 SD MMC 2 Data3 line in 4 8 bit mode or configured as card detection pin ma...

Page 28: ...ted Pin left unconnected 84D GND 0 Ground 0 V 85D X_I2C1_CLK I O VDD_3V3 I C 1 Serial Clock 86D X_CSPI1_MOSI I O VDD_3V3 SPI 1 Master data out slave data in 87D X_CSPI1_MISO I O VDD_3V3 SPI 1 Master d...

Page 29: ...f the solder jumpers on the board 13 solder jumpers are located on the top side of the module opposite side of connectors and 5 solder jumpers are located on the bottom side of the module connector si...

Page 30: ...phyCORE i MX35 22 PHYTEC Messtechnik GmbH 2010 L 734e_1 J23 J9 J5 J7 J24 J14 J21 J10 J1 J11 J12 J8 J15 PHYTEC PCM 043 Figure 6 Jumper Locations Top View...

Page 31: ...Jumpers PHYTEC Messtechnik GmbH 2010 L 734e_1 23 J22 J13 J4 J2 J3 Figure 7 Jumper Locations Bottom View...

Page 32: ...ash open NFRB signal from the i MX35x is not connected to R B1 pin of the NAND Flash J8 closed Connects NFRB signal from the i MX35x to R B3 pin of the NAND Flash open NFRB signal from the i MX35x is...

Page 33: ...Jumpers PHYTEC Messtechnik GmbH 2010 L 734e_1 25 J22 2 3 DS75 A1 is connected to VDD_3V3 high 1 2 DS75 A1 is connected to GND low...

Page 34: ...n Connect all VIN input pins to your power supply As a general design rule we recommend connecting all GND pins which are neighboring signals being used in the application circuitry The i MX35x CPU is...

Page 35: ...L 734e_1 27 5 Real Time Clock U1 Backup Voltage In case of a power fail or a user off event the backup voltage X_BKUP_SUPPLY provides power to the I C Real Time Clock U1 RTC8564JE In this case a backu...

Page 36: ...itialization via pin termination 6 1 System Startup Configuration During the reset cycle the i MX35 processor reads the state of selected controller signals to determine the basic system configuration...

Page 37: ...Boot Mode Device 0 0 Internal boot 1 0 External boot 1 1 Enter wait mode Table 5 Advanced Boot Modes of i MX35x Module Boot Mode Selection BOOT 4 BOOT 3 BOOT 2 BOOT 1 BOOT 0 Boot Mode Device 0 0 0 1 0...

Page 38: ...board memory DDR2 SDRAM 128MByte up to 256MByte NAND Flash 1GByte up to 32GByte NOR Flash 32MByte up to 64MByte I C EEPROM 32KB up to 32KByte It should be noted that the DDR2 SDRAM has a dedicated mem...

Page 39: ...0x9000 0000 0x9FFF FFFF CSD1 not used on phyCORE i MX35 0xA000 0000 0xA7FF FFFF WEIM CS0 flash 128 NOR Flash U9 0xA800 0000 0xAFFF FFFF WEIM CS1 flash 64 multiplexed with NANDF_CE3 0xB000 0000 0xB1FF...

Page 40: ...al CSD0 starting at 0x8000 0000 Actually there is no RAM bank 1 for the i MX35x So the CSD1 chip select line is freed and can be used as CS3 Typically the DDR2 SDRAM initialization is performed by a b...

Page 41: ...cated at memory address 0xA000 0000 The entire Flash can be write protected by pulling the x_ FL_WP signal located at the phyCORE connector X1 on pin 62B low The following NOR Flash devices can be use...

Page 42: ...URER NAND FLASH P N DENSITY MBYTE Numonyx NAND01G xxx 1024 Numonyx NAND02G xxx 2048 Additionally any parts that are footprint TSOP and functionally compatible with the NAND Flash devices listed above...

Page 43: ...E connector as X_I2C1_DAT on X1 pin 85C and X_I2C1_CLK on X1 pin 85D Three solder jumpers are provided to set the lower address bits J11 J14 and J15 Refer to section 7 5 1 for details on setting these...

Page 44: ...ress bits of the seven bit I C device address are configurable using jumpers J11 J14 and J15 J15 sets address bit A0 J14 address bit A1 and J11 address bit A2 Table 9 below shows the resulting seven b...

Page 45: ...the EEPROM U2 device Closing this jumper allows write access to the device while opening this jumper enables write protection The following configurations are possible Table 10 EEPROM Write Protection...

Page 46: ...ort while the TxD line of the transceiver is connected to the RxD line of the COM port The ground potential of the phyCORE i MX35 circuitry needs to be connected to the applicable ground pin on the CO...

Page 47: ...gnals to these same pins The standard phyCORE i MX35 module will have U12 populated thereby routing the RS 232 level signals to the phyCORE connector Be sure the phyCORE i MX35 configuration you are w...

Page 48: ...yCORE i MX35 USB OTG functionality The applicable interface signals D D VBUS ID can be found in the phyCORE connector pin out Table 1 Also the whole USB OTG interface is connected to the phyCORE conne...

Page 49: ...of the connected device and automatically configures the PHY TX and RX pins accordingly The Ethernet Phy also features LinkMD cable diagnostics which allows detection of common cabling plant problems...

Page 50: ...use the CAN functionality of the i MX35x you need an additional CAN transceiver and a CAN connector for each of the two CAN interfaces which are provided by the phyCORE i MX35 module Table 13 CAN Cont...

Page 51: ...CAN PHYTEC Messtechnik GmbH 2010 L 734e_1 43...

Page 52: ...external flash internal controller RAM or for debugging programs currently executing The JTAG interface extends out to a 2 0 mm pitch pin header at X2 on the edge of the module PCB Figure 8 and Figur...

Page 53: ...e The JTAG connector X2 only populates phyCORE i MX35 modules with order code PCM 043 D JTAG connector X2 is not populated on phyCORE modules with order code PCM 043 However all JTAG signals are also...

Page 54: ...ter extends the signals of the module s JTAG connector to a standard ARM connector with 2 54 mm pin pitch The JA 002 therefore functions as an adapter for connecting the module s non ARM compatible JT...

Page 55: ...JTAG Interface X2 PHYTEC Messtechnik GmbH 2010 L 734e_1 47...

Page 56: ...h a maximum component height of 4 1 mm on the bottom connector side of the PCB and approximately 3 25 mm on the top microcontroller side The board itself is approximately 1 25 mm thick 2 05mm D D 4 7m...

Page 57: ...ting voltage VIN 5 V Power consumption VIN 600 mA max Conditions VIN 5 V 32 MByte Flash 128 MB DDR2 RAM 1 GB NAND Flash Ethernet 532 MHz CPU frequency at 20 C These specifications describe the standar...

Page 58: ...e Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to...

Page 59: ...Hints for Handling PHYTEC Messtechnik GmbH 2010 L 734e_1 51...

Page 60: ...RE i MX35 module works with the phyCORE i MX Carrier Board how both boards are connected together over the phyMAPPER and you will also find all settings that have to be done for a speedy and secure st...

Page 61: ...fferent pinning it is necessary to map the signals of the modules to the right place on the Carrier Board For this every i MX module comes with a phyMAPPER that is mapping the signals of the i MX modu...

Page 62: ...odule connectors and i MX Carrier Board connector do not allow for direct connection of the phyCORE i MX modules into a single standardized Carrier Board To allow for the use of a single Carrier Board...

Page 63: ...The phyCORE i MX on the Development Board PHYTEC Messtechnik GmbH 2010 L 734e_1 55 X2 X2 X2 Figure 13 phyMAP i MX35 Bottom View...

Page 64: ...35 Mapper They are used to set different functions partially in relation with the i MX Carrier Board An individual description of the jumpers and a list of all jumper settings you will find subsequent...

Page 65: ...J6 This jumper selects where the signal X_USBH2_OC of the i MX35 is connected to If the USB Host interface of the phyMAP i MX35 mapper is used this jumper is set to 2 3 If the USB Host interface of th...

Page 66: ...PIO signal is used with the CAN interface on the mapper Table 15 Jumper Settings of PMA 005 JUMPER SETTING DESCRIPTION J1 open closed Battery charger path on PCM 970 not active Battery charger path on...

Page 67: ...old text Table 16 PMA 005 Mapping List SIGNAL NAME ON PMA 005 MAPPER X1 PIN MAPPED TO X2 PIN SIGNAL NAME ON I MX CARRIER BOARD A0_3V3 35B 27B x_A0 A1_3V3 36B 28A x_A1 A2_3V3 36A 28B x_A2 A3_3V3 37B 29...

Page 68: ...B x_ EB1 ECB_WAIT_3V3 33B 5E x_EXP006 LBA_3V3 34A 54A x_LBA VDD_ALIVE 1B 44E x_EXP069 VDD_1V8 61A 43E x_EXP067 X_BKUP_SUPPLY 6C 6C x_VBAT X_BOOT0 98C 53C x_BOOT_MODE0 X_BOOT1 99C 53D x_BOOT_MODE1 X_BO...

Page 69: ...O 87D 25E x_EXP038 X_CSPI1_MOSI 86D 24E x_EXP037 X_CSPI1_SCLK 86C 23E x_EXP035 X_CSPI1_SPI_RDY 89C 27F x_EXP042 X_CSPI1_SS0 88C 26F x_EXP041 X_CSPI1_SS1 88D 26E x_EXP040 X_CSPI2_MISO 90D 96B x_MISO X_...

Page 70: ...X_FSR 48C 73D x_EXP089 X_FST 44C 74C x_EXP090 X_FUSE_VDD 7D 6D x_iMX_FUSE X_GPIO2_6 96A 58C 76D X_LED x_EXP094 X_GPIO2_7 98A 38C 75D x_EXP092 X_GPIO2_23 99A 95A 77D x_SD_W x_EXP095 X_GPIO2_24 100A 94A...

Page 71: ...x_LC_D12 X_LCD_LD13 21A 21A x_LC_D13 X_LCD_LD14 21B 21B x_LC_D14 X_LCD_LD15 22B 22B x_LC_D15 X_LCD_LD16 23B 23B x_LC_D16 X_LCD_LD17 23A 23A x_LC_D17 X_LCD_LD18 24A 17F x_EXP026 X_LCD_LD19 25A 18F x_E...

Page 72: ...RT1_CTS 74C 61D x_CTS_DCE1_TTL X_UART1_DCD 76C 63D x_DCD_DCE1_TTL X_UART1_DSR 75D 63C x_DSR_DCE1_TTL X_UART1_DTR 76D 64C x_DTR_DCE1_TTL X_UART1_RI 75C 62D x_RI_DCE1_TTL X_UART1_RTS 73C 60D x_RTS_DCE1_...

Page 73: ...x_EXP059 X_USBPHY2_DP 57D 36E x_EXP056 X_VSTBY 2B 79C x_EXP098 CS0_3V3 28A 1E x_EXP000 CS1_3V3 29A 1F x_EXP001 CS3_3V3 28B 2F x_EXP002 CS4_3V3 30A 3E x_EXP003 CS5_3V3 30B 3F x_EXP004 OE_3V3 33A 53A x...

Page 74: ...ossibility to use the onboard USB Host interface with the phyCORE i MX35 module That s why Phytec decided to put a separate USB Host interface on the i MX35 mapper board This USB Host interface is pop...

Page 75: ...er Board is used USB Host on Mapper is used J7 1 2 2 3 USB Host on Carrier Board is used USB Host on Mapper is used J8 1 2 2 3 USB Host on Carrier Board is used USB Host on Mapper is used J9 1 2 2 3 U...

Page 76: ...e The i MX35x microcontroller provides two CAN controllers Because there is only one CAN interface available on the i MX Carrier Board Phytec designed a second CAN interface on the i MX35 mapper board...

Page 77: ...734e_1 69 Table 18 PMA 005 CAN Jumper Settings J10 1 2 2 3 X_SD2_DATA3 is mapped to PCM 970 CAN1 on Mapper is used J11 1 2 2 3 X_SD2_DATA2 is mapped to PCM 970 CAN1 on Mapper is used J12 1 2 2 3 X_SD...

Page 78: ...s able to boot from different devices as described in chapter 6 1 2 Boot Mode Select To have a choice from which device the controller should boot the boot signals BOOT0 to BOOT4 are connected to two...

Page 79: ...TEC Messtechnik GmbH 2010 L 734e_1 71 Table 19 x_BOOT3 Selection STATE OF SW NUMBER 1 STATE OF SW NUMBER 2 STATE OF X_BOOT3 ON OFF 1 OFF ON 0 Table 20 x_BOOT4 Selection STATE OF SW NUMBER 3 STATE OF S...

Page 80: ...PHYTEC Messtechnik GmbH 2010 L 734e_1 15 2 6 phyMAP i MX35 Mapper Physical Dimensions 77 37mm 20 78mm 1 18mm 50 6mm 9 76mm 107mm 13mm 4mm 70mm 50 6mm 26 35mm R3 L1 Figure 18 Physical Dimensions of phy...

Page 81: ...and phyCORE i MX Carrier Board In this chapter you will find specific information and settings to adapt the i MX Carrier Board to the i MX35 module For information about the general functionality of t...

Page 82: ...U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 X26 X27 X21 JP31 JP32 JP38 JP34 JP36 JP33 JP35 JP39 JP40 Figure 19 pyhCORE i M...

Page 83: ...y path JP33 1 2 3 4 Open Open No power switching direct supply from VCC_3V3 Separate supply path JP34 1 2 3 4 Open Open No power switching direct supply from VCC_3V3 Separate supply path JP35 Open Clo...

Page 84: ...en No power switching direct supply from VCC_3V3 Separate supply path JP34 1 2 3 4 Open Open No power switching direct supply from VCC_3V3 Separate supply path JP35 Open Closed VCC_5V Power Supply is...

Page 85: ...ly path JP34 1 2 3 4 Open Open No power switching direct supply from VCC_3V3 Separate supply path JP35 Open Closed VCC_5V Power Supply is enabled VCC_5V Power Supply is disabled JP36 Open Closed VCC_3...

Page 86: ...ble U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 JP7 JP8 JP10 P2 JP9 JP11 Figure 20 phyCORE i MX Carrier Board CAN Interface...

Page 87: ...gital Isolator is supplied by VCC_CAN Digital Isolator supply is VCC_5V JP9 1 2 2 3 CANV is connected to GND of i MX Carrier Board CANV is not connected to GND of i MX Carrier Board JP10 1 2 2 3 CANRx...

Page 88: ...R I A L 1 2 1 W I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging...

Page 89: ...yMAP i MX35 mapper With S5 on the i MX Carrier Board it is possible to select the status of BOOT0 BOOT1 and BOOT2 For detailed information see Table 25 Table 26 and Table 27 below Note A standard Boot...

Page 90: ...XK E Y B O A R D JTA G C A N U S B O TG S E R I A L 1 2 1 W I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line O U T Line I N M I C C H A R G E R G P I O V I N 3V 3...

Page 91: ...opment Board PHYTEC Messtechnik GmbH 2010 L 734e_1 83 15 3 5 Compact Flash Card Note Compact Flash Card is not supported by the phyCORE i MX35 module because there is no PCMCIA controller provided wit...

Page 92: ...ll B A C K U P LI C ell 5VD C3A D I S P LA Y M A TR I XK E Y B O A R D JTA G C A N U S B O TG S E R I A L 1 2 1 W I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line...

Page 93: ...s for i MX35 Module5 JUMPER SETTING DESCRIPTION JP50 2 3 1 2 MMC_WP signal of SD MMC Interface is connected to GPIO MMC_WP signal of SD MMC Interface is not connected to GPIO JP18 2 3 1 2 Level shifte...

Page 94: ...M C S D C A M E R A LC D S W R S 232 disable U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 X23 X13 X12 X11 JP24 JP23 JP20 JP...

Page 95: ...JP24 2 3 1 2 x_RXINR is connected to X13 LINE_OUTL is connected to X13 JP25 2 3 1 2 x_TSY1 is connected to X23 TP_Y is connected to X23 JP26 2 3 1 2 x_TSX2 is connected to X23 TP_X is connected to X2...

Page 96: ...W R S 232 disable U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 X17 JP45 JP46 JP44 JP6 J13 JP42 JP43 Figure 25 phyCORE iMX C...

Page 97: ...connected to GPIO2_0 Reset can be asserted JP42 1 2 2 3 USB Host is managed on the i MX baseboard USB Host is managed on the i MX module JP43 1 2 2 3 USB Host is managed on the i MX baseboard USB Host...

Page 98: ...M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 X22 X23 SW1 Figure 26 phyCORE i MX Carrier Board LCD Interfaces The phyCORE i MX35 module comes with a 2...

Page 99: ...MX on the Development Board PHYTEC Messtechnik GmbH 2010 L 734e_1 91 15 3 9 1 Serial LCD Note Serial LCD is not supported by the phyCORE i MX35 module because the i MX35x microcontroller does not prov...

Page 100: ...ell B A C K U P LI C ell 5VD C3A D I S P LA Y M A TR I XK E Y B O A R D JTA G C A N U S B O TG S E R I A L 1 2 1 W I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line...

Page 101: ...s of level shifter U12 are enabled CSI is active Outputs of U12 are disabled or GPIO x_CSI_ENABLE can be used to control U12 JP16 1 2 2 3 Jumper settings to chance camera sensor specific I C address F...

Page 102: ...phyCORE i MX35 94 PHYTEC Messtechnik GmbH 2010 L 734e_1 15 3 10 1 PHYTEC Camera Connector Note The phyCORE i MX35 module uses a 10 bit camera interface CSI_D6 to CSI_D15 at the Camera Connectors...

Page 103: ...D I S P LA Y M A TR I XK E Y B O A R D JTA G C A N U S B O TG S E R I A L 1 2 1 W I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line O U T Line I N M I C P H Y TE C...

Page 104: ...G Jumper Settings for phyCORE i MX35 Module8 JUMPER SETTING NAME DESCRIPTION closed Daisy chain ALL For common software debug High speed production JP12 open SJC only IEEE 1149 1 JTAG compatible mode...

Page 105: ...ble JP5 Open Closed Compact Flash is Slave Compact Flash is Master JP6 Open Closed USBH2 transceiver Reset is not controllable USBH2 transceiver Reset is controllable via GPIO JP7 1 2 2 3 CAN is manag...

Page 106: ...le JP24 1 2 2 3 Stereo LINE IN is managed on the baseboard Stereo LINE IN is managed on the module JP25 1 2 2 3 Touch screen is managed on the baseboard Touch screen is managed on the module JP26 1 2...

Page 107: ...ower enable managed on module JP43 1 2 2 3 USB VBUS overcurrent managed on the baseboard USB VBUS overcurrent managed on the module JP44 open closed USB Host is managed on the module USB Host is manag...

Page 108: ...in this manual 04 June 2009 Manual L 734e_0 PCM 043 PCB 1315 2 PMA 005 PCB 1318 2 PCM 970 PCB 1280 4 First draft Preliminary documentation Describes the phyCORE i MX35 with the i MX35 Mapper and the...

Page 109: ...Revision History PHYTEC Messtechnik GmbH 2010 L 734e_1 101...

Page 110: ...C70 R84 R69 XT2 L15 R78 C177 C97 U14 U1 U7 C171 R23 C84 C182 C13 L14 C89 TP9 C74 C113 U13 C33 XT3 C123 C106 R30 J10 C190 C102 L16 C94 R21 R40 C175 C25 C46 U16 R73 C112 C88 J1 R80 C77 R52 J11 TP5 R77...

Page 111: ...R41 U12 L6 C30 C35 C8 C59 C137 C118 R16 L1 C167 TP15 R18 C195 U3 C139 C5 R2 R11 C119 C56 R7 C170 C19 L2 R100 R96 C23 C151 J2 C21 J3 R42 U20 C2 R10 C16 R3 C26 C64 C37 C148 C71 R98 R82 R33 C100 C65 C22...

Page 112: ...I I C EEPROM 35 ISP1301 40 J J603 37 JA 002 45 JTAG Interface 43 JTAG Emulator Adapter 45 N NAND Flash 30 34 O Operating Temperature 47 Operating Voltage 47 P phyCORE connector 7 8 Physical Dimensions...

Page 113: ...ex PHYTEC Messtechnik GmbH 2010 L 734e_1 105 U U300 40 U301 38 U302 38 U600 34 U601 35 U602 32 33 U603 32 33 UART3 38 UART5 38 USB Device 40 USB Host 40 USB On The Go 40 USB OTG 40 W Weight 47 X X201...

Page 114: ...hyCORE i MX35 Document number L 734e_1 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Technologie Ho...

Page 115: ...Published by PHYTEC Messtechnik GmbH 2010 Ordering No L 734_1 Printed in Germany...

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