Phytec phyCORE-i.MX35, Hardware Manual

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phyCORE-i.MX35
98 
PHYTEC Messtechnik GmbH 2010 L-734e_1
JP16
1+2
2+3
CMOS-Sensor I²C address is 0x55
CMOS-Sensor I²C Address is 0x33
JP17
open
Closed
Compact Flash expansion connector is enabled
Compact Flash expansion connector is disabled
JP18
1+2
2+3
MMC driver is disabled
MMC driver is enabled
JP19
1+2
2+3
Stereo output is managed on the baseboard
Stereo output is managed on the module
JP20
1+2
2+3
Stereo output is managed on the baseboard
Stereo output is managed on the module
JP21
1+2
2+3
Stereo MIC is managed on the baseboard
Stereo MIC is managed on the module
JP22
1+2
2+3
Stereo MIC is managed on the baseboard
Stereo MIC is managed on the module
JP23
1+2
2+3
Stereo LINE IN is managed on the baseboard
Stereo LINE IN is managed on the module
JP24
1+2
2+3
Stereo LINE IN is managed on the baseboard
Stereo LINE IN is managed on the module
JP25
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP26
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP27
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP28
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP29
1+2
2+3
Backup voltage is supplied by ext. LICELL
Backup voltage is supplied by onboard Goldcap
JP30
1+2
3+4
5+6 VCC_BOOT is deep-sleep test voltage
VCC_CLK is deep-sleep test voltage
VCC_JTAG is deep-sleep test voltage
JP31
1+3,2+4
3+5,4+6
Power source is Power Over Ethernet (POE)
Power source is 5 V adapter
JP32
1+3,2+4
3+5,4+6
No power switching, direct supply of VCC_3V3
Separate supply path
JP33
1+2,3+4
Open,Open
No power switching, direct supply from VCC_3V3
Separate supply path