FP2 Analog Unit
Specifications
14 - 8
14.3 Table of Shared Memory Area
14.3 Table of Shared Memory Area
In the FP2 CPU unit with analog I/O, analog input unit, and analog output unit, in addition
to control of the analog input and output, shared memory that allows reading and writing
by the sequence program is stored.
14.3.1
Shared Memory of CPU Unit with Analog I/O
Address Descriptions
Initial value See section
10
Preparation completion flag for analog input ch 0 to 3
H0000
14.4.1
16
No execution of conversion processing setting for analog input ch 0 to 3 H1111
14.4.2
18
Range setting for analog input ch 0 and 1
HFFFF
14.4.3
19
Range setting for analog input ch 2 and 3
HFFFF
22
Average times setting for analog input ch 0
K1
14.4.4
23
Average times setting for analog input ch 1
K1
24
Average times setting for analog input ch 2
K1
25
Average times setting for analog input ch 3
K1
30
Offset changing setting for analog input ch 0
K0
14.4.5
31
Offset changing setting for analog input ch 1
K0
32
Offset changing setting for analog input ch 2
K0
33
Offset changing setting for analog input ch 3
K0
38
Analog output hold setting
H0000
14.5.1
39
Analog output hold (any value) data setting
K0000
14.5.2
42
Broken wire detection flag for temperature sensor input (TC, R.T.D)
H0000
14.4.6
Notes
D
Shared memory addresses other than those listed above are
not used. Do not perform reading and writing with addresses
that are not used. And the addresses 10 and 42 cannot be
written to using a user program.
D
The shared memory addresses are all preset when the power
is turned from off to on (they return to the initial values).
D
Addresses 16, 22 to 25, 30 to 33, 38, and 39 can be written to
by the program as many times as desired when the mode is
changed from the PROG. mode to the RUN mode.
D
Addresses 10 and 42 cannot be written to using a user
program. Reading is possible all the time.
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