NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
®
Cortex
®
-M0 Microcontroller
Aug, 2018
Page
121
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497
Rev 1.00
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MICRO
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UC02
9L
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UC029
S
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CHN
ICA
L R
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A
L
to set this bit again for next Power-down.
In Power-down mode, 4~24 MHz external high speed crystal oscillator and the 22.1184
MHz internal high speed RC oscillator will be disabled in this mode, but the 32.768 kHz
external low speed crystal oscillator and 10 kHz internal low speed oscillator are not
controlled by Power-down mode.
In Power- down mode, the PLL and system clock are disabled, and ignored the clock
source selection. The clocks of peripheral are not controlled by Power-down mode, if the
peripheral clock source is from 32.768 kHz external low speed crystal oscillator or the
internal 10 kHz low speed oscillator.
0 = Chip operating normally or chip in Idle mode because of WFI command.
1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI.
Note:
This bit is the protected bi
t, and programming it needs to write “59h”, “16h”, and
“88h” to address 0x5000_0100 to disable register protection. Refer to the register
REGWRPROT at address 0x100.
[6]
PD_WU_STS
Power-Down Mode Wake-Up Interrupt Status
Set by “Power-down wake-up event”, it indicates that resume from Power-down mode”
The flag is set if the GPIO, USB, UART, WDT, I
2
C, TIMER, BOD or RTC wake-up
occurred
Write 1 to clear the bit to 0.
Note:
This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
[5]
PD_WU_INT_EN
Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
0 = Power-down mode wake-up interrupt Disabled.
1 = Power-down mode wake-up interrupt Enabled.
Note1:
The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
Note2:
T
his bit is the protected bit, and programming it needs to write “59h”, “16h”, and
“88h” to address 0x5000_0100 to disable register protection. Refer to the register
REGWRPROT at address 0x100.
[4]
PD_WU_DLY
Wake-Up Delay Counter Enable Bit (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock
cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high
speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed
oscillator.
0 = Clock cycles delay Disabled.
1 = Clock cycles delay Enabled.
Note:
This bit is the protected bit, and programming it needs to write “59h”, “16h”, and
“88h” to address 0x5000_0100 to disable register protection. Refer to the register
REGWRPROT at address 0x100.
[3]
OSC10K_EN
10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Bit (Write Protect)
0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled.
1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled.
Note:
This bit is the protected bit, and programming it needs to write “59h”, “16h”, and
“88h” to address 0x5000_0100 to disable register protection. Refer to the register
REGWRPROT at address 0x100.
[2]
OSC22M_EN
22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Bit (Write Protect)
0 = 22.1184 MHz internal high speed RC oscillator (HIRC) Disabled.
1 = 22.1184 MHz internal high speed RC oscillator (HIRC) Enabled.
Note:
This bit is the protect
ed bit, and programming it needs to write “59h”, “16h”, and
“88h” to address 0x5000_0100 to disable register protection. Refer to the register
REGWRPROT at address 0x100.
[1]
XTL32K_EN
32.768 KHz External Low Speed Crystal Oscillator (LXT) Enable Bit (Write Protect)
0 = 32.768 kHz external low speed crystal oscillator (LXT) Disabled.
