Nuvoton NuMicro NUC029 Series, Technical Reference Manual, Page: 225 / 497

NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
®
Cortex
®
-M0 Microcontroller
Aug, 2018 Page 225 of 497
Rev 1.00
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UC02
9L
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UC029
S
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CHN
ICA
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PDMA Global Control Register (PDMA_GCRCSR)
Register Offset R/W Description Reset Value
PDMA_GCRCSR PDMA0x00 R/W PDMA Global Control Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved CRC_CLK_EN
23 22 21 20 19 18 17 16
Reserved CLK8_EN
15 14 13 12 11 10 9 8
CLK7_EN CLK6_EN CLK5_EN CLK4_EN CLK3_EN CLK2_EN CLK1_EN CLK0_EN
7 6 5 4 3 2 1 0
Reserved
Bits Description
[31:25] Reserved Reserved.
[24] CRC_CLK_EN
CRC Controller Clock Enable Bit
0 = Disabled.
1 = Enabled.
[23:17] Reserved Reserved.
[16] CLK8_EN
PDMA Controller Channel 8 Clock Enable Bit
0 = Disabled.
1 = Enabled.
[15] CLK7_EN
PDMA Controller Channel 7 Clock Enable Bit
0 = Disabled.
1 = Enabled.
[14] CLK6_EN
PDMA Controller Channel 6 Clock Enable Bit
0 = Disabled.
1 = Enabled.
[13] CLK5_EN
PDMA Controller Channel 5 Clock Enable Bit
0 = Disabled.
1 = Enabled.
[12] CLK4_EN
PDMA Controller Channel 4 Clock Enable Bit
0 = Disabled.
1 = Enabled.
[11] CLK3_EN
PDMA Controller Channel 3 Clock Enable Bit
0 = Disabled.
1 = Enabled.