NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
®
Cortex
®
-M0 Microcontroller
Aug, 2018
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Rev 1.00
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[21]
FIFO
FIFO Mode EnableBit
0 = FIFO mode Disabled.
1 = FIFO mode Enabled.
Note1:
Before enabling FIFO mode, the other related settings should be set in advance.
Note2:
In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1
automatically after writing data to the transmit FIFO buffer; the GO_BUSY bit will be
cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit
FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be
cleared to 0.
Note3:
After clearing this bit to 0, user must wait for at least 2 peripheral clock periods
before setting this bit to 1 again.
[20]
Reserved
Reserved.
[19]
REORDER
Byte Reorder Function EnableBit
0 = Byte Reorder function Disabled.
1 = Byte Reorder function Enabled. A byte suspend interval will be inserted among each
byte. The period of the byte suspend interval depends on the setting of SP_CYCLE.
Note1:
Byte Reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32
bits.
Note2:
In Slave mode with level-trigger configuration, the slave select pin must be kept at
active state during the byte suspend interval.
Note3:
The Byte Reorder function is not supported when the variable bus clock function or
Dual I/O mode is enabled.
[18]
SLAVE
Slave Mode EnableBit
0 = Master mode.
1 = Slave mode.
[17]
IE
Unit Transfer Interrupt EnableBit
0 = SPI unit transfer interrupt Disabled.
1 = SPI unit transfer interrupt Enabled.
[16]
IF
Unit Transfer Interrupt Flag
0 = No transaction has been finished since this bit was cleared to 0.
1 = SPI controller has finished one unit transfer.
Note:
This bit will be cleared by writing 1 to itself.
[15:12]
SP_CYCLE
Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive
transmit/receive transaction in a transfer. The definition of the suspend interval is the
interval between the last clock edge of the preceding transaction word and the first clock
edge of the following transaction word. The default value is 0x3. The period of the suspend
interval is obtained according to the following equation.
(SP_CYCLE[3:0] + 0.5) * period of SPI bus clock cycle
Example:
SP_CYCLE = 0x0 …. 0.5 SPI bus clock cycle.
SP_CYCLE = 0x1 …. 1.5 SPI bus clock cycles.
……
SP_CYCLE = 0xE …. 14.5 SPI bus clock cycles.
SP_CYCLE = 0xF …. 15.5 SPI bus clock cycles.
If the variable clock function is enabled and the transmit FIFO buffer is not empty, the
minimum period of suspend interval between the successive transactions is (6.5 +
SP_CYCLE) * SPI bus clock cycle.
[11]
CLKP
Clock Polarity