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NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
®
Cortex
®
-M0 Microcontroller
Aug, 2018
Page
446
of
497
Rev 1.00
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U
MICRO
®
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UC02
9L
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/N
UC029
S
E
E
T
E
CHN
ICA
L R
E
F
E
R
E
NC
E
M
A
NU
A
L
Note:
This bit will be cleared by writing 1 to itself.
[19:17]
Reserved
Reserved.
[16]
IF
SPI Unit Transfer Interrupt Flag
It is a mutual mirror bit of SPI_CNTRL[16].
0 = No transaction has been finished since this bit was cleared to 0.
1 = SPI controller has finished one unit transfer.
Note:
This bit will be cleared by writing 1 to itself.
[15:12]
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
[11]
SLV_START_INT
STS
Slave Start Interrupt Status
It is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror
bit of SPI_CNTRL2[11].
0 = Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to
1.
1 = A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is
done or by writing 1 to this bit
.
[10:5]
Reserved
Reserved.
[4]
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)
0 = The valid data count within the transmit FIFO buffer is larger than the setting value of
TX_THRESHOLD.
1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting
value of TX_THRESHOLD.
Note:
If TX_INTEN = 1 and TX_INTSTS = 1, the SPI controller will generate a SPI
interrupt request.
[3]
Reserved
Reserved.
[2]
RX_OVERRUN
Receive FIFO Overrun Status
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be
set to 1.
Note:
This bit will be cleared by writing 1 to itself.
[1]
Reserved
Reserved.
[0]
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)
0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting
value of RX_THRESHOLD.
1 = The valid data count within the receive FIFO buffer is larger than the setting value of
RX_THRESHOLD.
Note:
If RX_INTEN = 1 and RX_INTSTS = 1, the SPI controller will generate a SPI
interrupt request.