NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
®
Cortex
®
-M0 Microcontroller
Aug, 2018
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6.2.9.2 System Timer Control Register Description
SysTick Control and Status (SYST_CSR)
Register
Offset
R/W
Description
Reset Value
SYST_CSR
0x10
R/W
SysTick Control and Status Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
COUNTFLAG
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
CLKSRC
TICKINT
ENABLE
Bits
Description
[31:17]
Reserved
Reserved.
[16]
COUNTFLAG
Returns 1 If Timer Counted To 0 Since Last Time This Register Was Read
COUNTFLAG is set by a count transition from 1 to 0.
COUNTFLAG is cleared on read or by a write to the Current Value register.
[15:3]
Reserved
Reserved.
[2]
CLKSRC
System Tick Clock Source Selection
If CLKSRC(SYST_CSR[2]) = 1, SysTick clock source is from HCLK.
If CLKSRC(SYST_CSR[2]) = 0, SysTick clock source is defined by
STCLK_S(CLKSEL0[5:3]).
0 = Clock source is (optional) external reference clock.
1 = Core clock used for SysTick.
[1]
TICKINT
System Tick Interrupt Enabled
0 = Counting down to 0 does not cause the SysTick exception to be pended. Software can
use COUNTFLAG to determine if a count to 0 has occurred.
1 = Counting down to 0 will cause the SysTick exception to be pended. Clearing the
SysTick Current Value register by a write in software will not cause SysTick to be pended.
[0]
ENABLE
System Tick Counter Enabled
0 = Counter Disabled.
1 = Counter will operate in a multi-shot manner.