NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
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Cortex
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-M0 Microcontroller
Aug, 2018
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RX_FULL flag will be set to 1. The SPI controller will stop receiving data until the SPI_RX0
register is read by software.
In Slave mode, when the FIFO bit is set as 1, the GO_BUSY bit will be set as 1 by hardware
automatically.
In Slave mode, during transmission operation, when data is written to the SPI_TX0 register by
software, the data will be loaded into transmit FIFO buffer and the TX_EMPTY flag will be set to
0. The transmission will start when the slave device receives clock signal from master. Data can
be written to SPI_TX0 register as long as the TX_FULL flag is 0. After all data have been drawn
out by the SPI transmission logic unit and the SPI_TX0 register is not updated by software, the
TX_EMPTY flag will be set to 1.
In Slave mode, during receiving operation, the serial data is received from SPIn_MOSI0/1 pin and
stored to SPI_RX0 register. The reception mechanism is similar to Master mode reception
operation.
6.15.5.9 Interrupt
SPI unit transfer interrupt
As the SPI controller finishes a unit transfer, the unit transfer interrupt flag IF (SPI_CNTRL[16])
will be set to 1. The unit transfer interrupt event will generate an interrupt to CPU if the unit
transfer interrupt enable bit IE (SPI_CNTRL[17]) is set. The unit transfer interrupt flag can be
cleared only by writing 1 to it.
SPI Slave 3-wire mode start interrupt
In 3-wire mode, the slave 3-wire mode start interrupt flag, SLV_START_INTSTS, will be set to 1
when the slave senses the SPI clock signal. The SPI controller will issue an interrupt if the
SSTA_INTEN is set to 1. If the count of the received bits is less than the setting of TX_BIT_LEN
and there is no more SPI clock input over the expected time period which is defined by the user,
the user can set the SLV_ABORT bit to abort the current transfer. The unit transfer interrupt flag,
IF, will be set to 1 if the software set the SLV_ABORT bit.
Receive FIFO time-out interrupt
In FIFO mode, there is a time-out function to inform user. If there is a received data in the FIFO
and it is not read by software over 64 SPI peripheral clock periods in Master mode or over 576
SPI peripheral clock periods in Slave mode, it will send a time-out interrupt to the system if the
time-out interrupt enable bit, FIFO_CTL[21], is set to 1.
Transmit FIFO interrupt
In FIFO mode, if the valid data count of the transmit FIFO buffer is less than or equal to the
setting value of TX_THRESHOLD, the transmit FIFO interrupt flag will be set to 1. The SPI
controller will generate a transmit FIFO interrupt to the system if the transmit FIFO interrupt
enable bit, SPI_FIFO_CTL[3], is set to 1.
Receive FIFO interrupt
In FIFO mode, if the valid data count of the receive FIFO buffer is larger than the setting value of
RX_THRESHOLD, the receive FIFO interrupt flag will be set to 1. The SPI controller will generate
a receive FIFO interrupt to the system if the receive FIFO interrupt enable bit, SPI_FIFO_CTL[2],
is set to 1.
6.15.6 Timing Diagram
The active state of slave select signal can be defined by setting the SS_LVL (SPI_SSR[2]) and
SS_LTRIG (SPI_SSR[4]). The SPI clock which is in idle state can be configured as high or low
state by setting the CLKP (SPI_CNTRL[11]). It also provides the bit length of a transaction word in