Nuvoton NuMicro NUC029 Series, Technical Reference Manual, Page: 445 / 497

NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
®
Cortex
®
-M0 Microcontroller
Aug, 2018 Page 445 of 497
Rev 1.00
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UC029
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SPI Status Register (SPI_STATUS)
Register Offset R/W Description Reset Value
SPI_STATUS 0x44 R/W SPI Status Register 0x0500_0000
31 30 29 28 27 26 25 24
TX_FIFO_COUNT TX_FULL TX_EMPTY RX_FULL RX_EMPTY
23 22 21 20 19 18 17 16
Reserved TIMEOUT Reserved IF
15 14 13 12 11 10 9 8
RX_FIFO_COUNT
SLV_START
_INTSTS
Reserved
7 6 5 4 3 2 1 0
Reserved TX_INTSTS Reserved
RX_
OVERRUN
Reserved RX_INTSTS
Bits Description
[31:28] TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
[27] TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)
It is a mutual mirror bit of SPI_CNTRL[27].
0 = Transmit FIFO buffer is not full.
1 = Transmit FIFO buffer is full.
[26] TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
It is a mutual mirror bit of SPI_CNTRL[26].
0 = Transmit FIFO buffer is not empty.
1 = Transmit FIFO buffer is empty.
[25] RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)
It is a mutual mirror bit of SPI_CNTRL[24].
0 = Receive FIFO buffer is not empty.
1 = Receive FIFO buffer is empty.
[24] RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
It is a mutual mirror bit of SPI_CNTRL[24].
0 = Receive FIFO buffer is not empty.
1 = Receive FIFO buffer is empty.
[23:21]
Reserved
Reserved.
[20] TIMEOUT
Time-Out Interrupt Flag
0 = No receive FIFO time-out event.
1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over
64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave
mode. When the received FIFO buffer is read by software, the time-out status will be
cleared automatically.