Nuvoton NuMicro NUC029 Series, Technical Reference Manual, Page: 186 / 497

NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
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Cortex
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-M0 Microcontroller
Aug, 2018 Page 186 of 497
Rev 1.00
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GPIO Port [A/B/C/E/F] Data Output Write Mask Register (GPIOx _DMASK)
Register Offset R/W Description Reset Value
GPIOA_DMASK 0x00C R/W GPIO Port A Data Output Write Mask Register 0x0000_0000
GPIOB_DMASK
0x04C R/W GPIO Port B Data Output Write Mask Register 0x0000_0000
GPIOC_DMASK 0x08C R/W GPIO Port C Data Output Write Mask Register 0x0000_0000
GPIOE_DMASK 0x10C R/W GPIO Port E Data Output Write Mask Register 0x0000_0000
GPIOF_DMASK 0x14C R/W GPIO Port F Data Output Write Mask Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
DMASK
7 6 5 4 3 2 1 0
DMASK
Bits Description
[31:16] Reserved
Reserved.
[n]
n = 0,1..15
DMASK[n]
Port [A/B/C/E/F] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When
the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the
write signal is masked, write data to the protect bit is ignored
0 = Corresponding GPIOx_DOUT[n] bit can be updated.
1 = Corresponding GPIOx_DOUT[n] bit protected.
Note1: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not
protect the corresponding bit control register (PAn_PDIO, PBn_PDIO, PCn_PDIO,
PEn_PDIO and PFn_PDIO).
Note2: Max. n = 15 for GPIOA/GPIOB/GPIOC; n = 5 for GPIOE; Max. n = 1 for GPIOF.
Note3: The PA.7, PB.12, PC.4, PC.5, PC.12, PC.13 pin is ignored.