NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
®
Cortex
®
-M0 Microcontroller
Aug, 2018
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Rev 1.00
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SPI Control and Status Register 2 (SPI_CNTRL2)
Register
Offset
R/W
Description
Reset Value
SPI_CNTRL2
0x3C
R/W
Control and Status Register 2
0x0000_1000
31
30
29
28
27
26
25
24
BCn
Reserved
23
22
21
20
19
18
17
16
Reserved
SS_INT_OPT
15
14
13
12
11
10
9
8
Reserved
DUAL_
IO_EN
DUAL_
IO_DIR
SLV_START
_INTSTS
SSTA_
INTEN
SLV_ABORT
NOSLVSEL
7
6
5
4
3
2
1
0
Reserved
Bits
Description
[31]
BCn
SPI Peripheral Clock Backward Compatible Option
0 = Backward compatible clock configuration.
1 = Clock configuration is not backward compatible.
Refer to the description of SPI_DIVIDER register for details.
[30:17]
Reserved
Reserved.
[16]
SS_INT_OPT
Slave Select Inactive Interrupt Option
This setting is only available if the SPI controller is configured as level trigger
slave device.
0 = As the slave select signal goes to inactive level, the IF bit will NOT be set to 1.
1 = As the slave select signal goes to inactive level, the IF bit will be set to 1.
[15:14]
Reserved
Reserved.
[13]
DUAL_IO_EN
Dual I/O Mode EnableBit
0 = Dual I/O mode Disabled.
1 = Dual I/O mode Enabled.
[12]
DUAL_IO_DIR
Dual I/O Mode Direction Control
0 = Dual Input mode.
1 = Dual Output mode.
[11]
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status
This bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual
mirror bit of SPI_STATUS[11].
0 = Slave has not detected any SPI clock transition since the SSTA_INTEN bit
was set to 1.
1 = A transaction has started in Slave 3-wire mode. It will be cleared automatically
when a transaction is done or by writing 1 to this bit.