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User’s Manual U11969EJ3V0UM00
CHAPTER 4 BUS CONTROL FUNCTION
(7) Bus hold timing
Remarks 1.
indicates the sampling timing.
2. The dotted line indicates the high-impedance state.
Caution
When the bus hold state is entered after the write cycle, a high-level signal may be briefly
output from the R/W pin immediately before the HLDAK signal changes from the high
level to the low level.
CLKOUT
R/W
DSTB,
RD,
WRL,
WRH
UBEN,
LBEN
WAIT
HLDRQ
T2
T3
TH
TH
TH
TH
TI
T1
HLDAK
A16 to A23
AD0 to AD15
Address
Address
Data
Address
ASTB
Undefined
Undefined
Undefined
Address
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