NEC V854 UPD703006, User Manual

Page: 138 / 417

138
User’s Manual U11969EJ3V0UM00
CHAPTER 6 CLOCK GENERATOR FUNCTION
The sequence of setting data in this register is the same as the power save control register (PSC). However, the
limitation items listed in Cautions 2 for the 3.4.9 Specific registers do not apply. For details, refer to 6.5.2 Control
register.
(1) Example of settings
The example of settings is as below.
Operation Mode
Pins CKC Register
Input Clock Internal System
CKSEL PLLSEL CKDIV1 CKDIV0
(f
XX
) Clock (
φ
)
Direct mode H Note 0 0 16 MHz 8 MHz
PLL mode (1-x L L 0 0 33 MHz 33 MHz
multiplication)
L L 1 0 33 MHz 6.6 MHz
L L 1 1 33 MHz 3.3 MHz
PLL mode (5-x L H 0 0 6.6 MHz 33 MHz
multiplication)
L H 1 0 6.6 MHz 6.6 MHz
L H 1 1 6.6 MHz 3.3 MHz
Other than the above Setting prohibited
Note Connect directly to V
DD
or V
SS
.
Remark H : High level input
L : Low level input