NEC V854 UPD703006 User Manual Download Page 153

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User’s Manual U11969EJ3V0UM00

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CHAPTER 6 CLOCK GENERATOR FUNCTION

The PSC register reset value is 00H in ROMless mode 1 and 2 and single-chip mode 2 and C0H in single-chip

mode 1 and PROM mode. Therefore, the CLKOUT signal is output during the reset period in ROMless mode 1 and

2 and single-chip mode 2. In single-chip mode 1, the CLKOUT signal is not output until the DCLK1 and DCLK0 bits

of the PSC register are set to “11” after reset is released (low level output).

In the PROM mode, the CLKOUT signal is not output (low level output).

6.7.3 CLO signal output control

The clock to be output to CLO pin can be selected by the FS bit of the CLOM register.

CLO pin outputs a signal which has the same level as that of the LV bit when the CLE bit is 0. Signal is output

synchronized with the clock (the frequency selected by the FS bit ) immediately after the CLE bit is set to 1.

Then, if the CLE bit is set to 0, the same level as that of the LV bit is output, and the output operation thereafter

is stopped.

Figure 6-2. CLO Signal Output Timing

(a) When LV = 0

(b) When LV = 1

Remark

n = 1, 2, 4, 8, 16

CLO

CLE

CLO

CLE

Summary of Contents for V854 UPD703006

Page 1: ...Manual Printed in Japan 1997 V854TM 32 16 Bit Single Chip Microcontroller Hardware µPD703006 µPD703008 µPD70F3008 µPD703008Y µPD70F3008Y Document No U11969EJ3V0UM00 3rd edition Date Published March 1999 N CP K ...

Page 2: ...2 User s Manual U11969EJ3V0UM00 MEMO ...

Page 3: ...input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins...

Page 4: ...iability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality g...

Page 5: ...esseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58...

Page 6: ...n to the item High transfer speed in 8 3 1 Features p 241 Addition of Note to bits 4 and 5 in 8 4 4 3 IIC clock selection register IICCL p 242 Addition of Caution to 8 4 4 4 IIC shift register IIC p 276 Addition of 8 4 6 15 b Operation during communication reservation when a multi master is used c Start operation after communication reservation when a multi master is used and d STT setting timing ...

Page 7: ...electrical engineering logic circuits and microcontrollers To find out the details of a register whose the name is known Refer to APPENDIX A REGISTER INDEX To findout the details of a function whose name is known Refer to APPENDIX C INDEX To understand the details of an instruction function Refer to the V850 Family Architecture User s Manual available separately To understand the overall functions...

Page 8: ...evelopment tools User s Manual Document Name Document No IE 703002 MC In circuit emulator U11595E IE 703008 MC EM1 In circuit emulator option board U12420E CA850 C Compiler Package Operation UNIXTM based U12839E Operation WindowsTM based U12827E C Language U12840E Assembly Language U10543E ID850 Ver 1 31 Integrated Debugger Operation Windows based U13716E RX850 Real Time OS Basics U13430E Technica...

Page 9: ...IONS 49 3 1 Features 49 3 2 CPU Register Set 50 3 2 1 Program register set 51 3 2 2 System register set 52 3 3 Operation Modes 54 3 3 1 Operation modes 54 3 3 2 Specifying operation mode 54 3 4 Address Space 56 3 4 1 CPU address space 56 3 4 2 Image Virtual Address Space 57 3 4 3 Wrap around of CPU address space 58 3 4 4 Memory map 59 3 4 5 Area 60 3 4 6 External expansion mode 67 3 4 7 Recommende...

Page 10: ...eatures 99 5 2 Non Maskable Interrupt 102 5 2 1 Operation 103 5 2 2 Restore 105 5 2 3 Non maskable interrupt status flag NP 106 5 2 4 Noise elimination circuit of NMI pin 106 5 2 5 Edge detection function of NMI pin 106 5 3 Maskable Interrupts 107 5 3 1 Operation 109 5 3 2 Restore 111 5 3 3 Priorities of maskable interrupts 112 5 3 4 Interrupt control register xxICn 116 5 3 5 In service priority r...

Page 11: ...guration 152 6 7 2 CLKOUT signal output control 152 6 7 3 CLO signal output control 153 CHAPTER 7 TIMER COUNTER FUNCTION REAL TIME PULSE UNIT 157 7 1 Features 157 7 2 Basic Configuration 158 7 2 1 Timer 0 161 7 2 2 Timer 1 162 7 2 3 Timer 2 164 7 2 4 Timer 3 165 7 3 Control Register 166 7 4 Timer 0 Operation 174 7 4 1 Count operation 174 7 4 2 Count clock selection 175 7 4 3 Overflow 176 7 4 4 Cle...

Page 12: ...d Serial Interface 0 to 3 CSI0 to CSI3 220 8 3 1 Features 220 8 3 2 Configuration 220 8 3 3 Control registers 222 8 3 4 Basic operation 224 8 3 5 Transmission in CSI0 to CSI3 226 8 3 6 Reception in CSI0 to CSI3 227 8 3 7 Transmission reception in CSI0 to CSI3 228 8 3 8 System configuration example 230 8 4 I2 C Bus µPD703008Y and 70F3008Y only 231 8 4 1 Features 231 8 4 2 Functions 232 8 4 3 Config...

Page 13: ...ons 319 9 8 1 Stop of conversion operations 319 9 8 2 Interval of the external timer trigger 319 9 8 3 Operation in the standby mode 319 9 8 4 Compare coincide interrupt in the timer trigger mode 319 CHAPTER 10 REAL TIME OUTPUT FUNCTION 321 10 1 Configuration and Function 321 10 2 Control Register 322 10 3 Operation 322 10 4 Example 323 CHAPTER 11 PWM UNIT 325 11 1 Features 325 11 2 Configuration ...

Page 14: ...14 4 Communication System 385 14 5 Pin Handling 386 14 5 1 VPP pin 387 14 5 2 Serial interface pin 388 14 5 3 Reset pin 390 14 5 4 NMI pin 390 14 5 5 Mode pin 390 14 5 6 Port pin 390 14 5 7 Other signal pin 390 14 5 8 Power supply 390 14 6 Programming Method 391 14 6 1 Flash memory control 391 14 6 2 Flash memory programming mode 392 14 6 3 Selection of communication mode 392 14 6 4 Communication ...

Page 15: ...15 User s Manual U11969EJ3V0UM00 APPENDIX A REGISTER INDEX 397 APPENDIX B INSTRUCTION SET LIST 403 APPENDIX C INDEX 409 ...

Page 16: ...Interrupt Requests Simultaneously Generated 115 5 9 Example of Noise Elimination Timing 119 5 10 Software Exception Processing 126 5 11 RETI Instruction Processing 127 5 12 Exception Trap Processing 129 5 13 RETI Instruction Processing 130 5 14 Pipeline Operation at Interrupt Request Acknowledge General Description 133 6 1 Block Configuration 151 6 2 CLO Signal Output Timing 153 7 1 Basic Operatio...

Page 17: ...Output Timing 198 7 28 Example of PWM Output Programming Procedure 199 7 29 Example of Interrupt Request Processing Routine Modifying Compare Value 200 7 30 Example of Frequency Measurement Timing 201 7 31 Example of Set up Procedure for Frequency Measurement 202 7 32 Example of Interrupt Request Processing Routine Calculating Cycle 202 8 1 Block Diagram of Asynchronous Serial Interface 208 8 2 Fo...

Page 18: ...6 9 6 Example of 1 Buffer Mode A D trigger select 1 buffer Operation 308 9 7 Example of 4 Buffer Mode A D trigger select 4 buffer Operation 309 9 8 Example of Scan Mode A D trigger scan Operation 310 9 9 Example of 1 Buffer Mode timer trigger select 1 buffer Operation 312 9 10 Example of Operation in 4 Buffer Mode timer trigger select 4 buffer 313 9 11 Example of Scan Mode timer trigger scan Opera...

Page 19: ...Diagram of Type B 342 12 3 Block Diagram of Type C 343 12 4 Block Diagram of Type D 343 12 5 Block Diagram of Type E 344 12 6 Block Diagram of Type F 344 12 7 Block Diagram of Type G 345 12 8 Block Diagram of Type H 345 12 9 Block Diagram of Type I 346 12 10 Block Diagram of Type J 346 12 11 Block Diagram of Type K 347 ...

Page 20: ...ority of Interrupts 215 8 2 I2 C Bus Configuration 234 8 3 INTIIC Generation Timing and Wait Control 270 8 4 Definition of Extension Code Bit 271 8 5 Wait Time 273 8 6 Baud Rate Generators 0 to 3 Set up Values when typical clocks are used 289 9 1 Correspondence between Analog Input Pin and ADCRn Register 1 buffer mode A D trigger select 1 buffer 308 9 2 Correspondence between Analog Input Pin and ...

Page 21: ...CRn Register 4 buffer mode external trigger select 4 buffer 317 9 9 Correspondence between Analog Input Pin and ADCRn Register scan mode external trigger scan 318 13 1 Operating Status of I O and Output Pins During Reset Period 378 13 2 Initial Values after Reset of Each Register 380 14 1 List of Communication Systems 392 ...

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Page 23: ...hardware multiplier saturated operation instructions and bit manipulation instructions that are ideal for digital servo control applications in addition to the basic instructions that have a high real time response speed and can be executed in 1 clock cycle This microcontroller can be employed for many applications including real time control systems such as AV applications including digital still...

Page 24: ... Idle state insertion function External bus interface 16 bit data bus address data multiplexed Bus hold function External wait function Internal memory Part Number Internal ROM Internal RAM µPD703006 None 4 Kbytes µPD703008 128 K Mask ROM 4 Kbytes 703008Y µPD70F3008 128 K Flash memory 4 Kbytes 70F3008Y Interrupt exception External interrupt 22 including NMI Internal interrupt 31 sources Exception ...

Page 25: ...servo camera control of camera built in VCRs etc Portable cameras such as digital still cameras etc Portable telephones and portable information terminals etc 1 4 Ordering Information Part number Package Internal ROM µPD703006GJ 33 8EU 144 pin plastic LQFP fine pitch 20 20 mm None µPD703008GJ 25 8EU 144 pin plastic LQFP fine pitch 20 20 mm Mask ROM µPD703008YGJ 25 8EU 144 pin plastic LQFP fine pit...

Page 26: ...HLDRQ P95 HLDAK P94 ASTB P93 DSTB RD P92 R W WRH P91 UBEN P90 LBEN WRL P67 A23 P66 A22 P65 A21 P64 A20 P63 A19 P62 A18 P61 A17 P60 A16 VSS P57 AD15 P56 AD14 P55 AD13 P54 AD12 P53 AD11 P52 AD10 P51 AD9 P50 AD8 P47 AD7 P46 AD6 P45 AD5 P44 AD4 P43 AD3 P42 AD2 P41 AD1 P40 AD0 VDD V SS NC V PP Note 3 V DD MODE0 MODE1 MODE2 Note 4 P140 P141 P142 P143 P144 P145 P146 P147 P100 PWM0 P101 PWM1 P102 PWM2 P10...

Page 27: ...o TI24 TO00 TO01 Timer Output TO20 to TO24 TXD Transmit Data UBEN Upper Byte Enable VDD Power Supply VPP Programming Power Supply VSS Ground WAIT Wait WRH Write Strobe High Level Data WRL Write Strobe Low Level Data X1 X2 Crystal Pin name A16 to A23 Address Bus AD0 to AD15 Address Data Bus ADTRG AD Trigger Input ANI0 to ANI15 Analog Input ASTB Address Strobe AVDD Analog VDD AVREF Analog Reference ...

Page 28: ...CPU PC 32 bit barrel shifter System register General register 32 bits x 32 ALU Multiplier 16 x 16 32 Port P140 to P147 P130 to P137 P120 to P127 P110 to P117 P100 to P103 P90 to P96 P80 to P87 P70 to P77 P60 to P67 P50 to P57 P40 to P47 P30 to P36 P21 to P26 P20 P10 to P17 P00 to P07 CG BCU Instruction queue ASTB DSTB R W UBEN LBEN WAIT A16 to A23 AD0 to AD15 HLDRQ HLDAK RD WRL WRH VDD VSS CVDD CV...

Page 29: ...his RAM can be accessed in 1 clock by the CPU when data is accessed 5 Interrupt controller INTC Processes interrupt requests NMI INTP00 to INTP05 INTP10 to INTP14 INTP20 to INTP24 INTP30 and INTP50 to INTP53 from the internal peripheral hardware and external sources Eight levels of priorities can be specified for these interrupt requests and multiplexed processing control can be performed on an in...

Page 30: ...tput Port11 8 bit I O Timer I O external interrupt Port12 Serial interface Port13 Real time output port Port14 10 PWM Pulse Width Modulation The V854 is provided with four channels of PWM signal output for which the 12 to 16 bit resolutions can be selected The PWM output can be used as a D A converter output by connecting an external low pass filter It is suitable for controlling the actuator of m...

Page 31: ...TP30 P22 ADTRG P23 INTP50 P24 INTP51 P25 INTP52 P26 INTP53 P30 I O SO0 TXD P31 SI0 RXD P32 SCK0 P33 SO1 SDA P34 SI1 P35 SCK1 SCL P36 P40 to P47 I O AD0 to AD7 Port 2 P20 is input only port This pin operates as NMI input when valid edge is input Bit 0 in P2 register signifies NMI input state P21 to P26 are 6 bit input output port pins Can be specified in input output mode in 1 bit units Port 3 7 bi...

Page 32: ...24 INTP24 P120 I O SO2 P121 SI2 P122 SCK2 P123 SO3 P124 SI3 P125 SCK3 P126 P127 CLO P130 to P137 I O RTP0 to RTP7 P140 to P147 I O Port 5 8 bit I O port Can be specified in input output mode in 1 bit units Port 14 8 bit I O port Can be specified in input output mode in 1 bit units Port 7 8 bit input only port Port 8 8 bit input only port Port 9 7 bit I O port Can be specified in input output mode ...

Page 33: ...nal maskable interrupt request input P06 TCLR0 INTP05 P07 TI0 INTP10 to INTP13 Input P10 to P13 INTP14 Input External maskable interrupt request input P14 TI1 INTP20 Input External maskable interrupt request input P16 TI20 INTP21 P111 TI21 INTP22 P113 TI22 INTP23 P115 TI23 INTP24 P117 TI24 INTP30 Input P21 INTP50 to INTP53 Input External maskable interrupt request input P23 to P26 NMI Input Non ma...

Page 34: ...gher address bus when external memory is used P60 to P67 LBEN Output Lower byte enable signal output of external data bus P90 WRL UBEN Higher byte enable signal output of external data bus P91 R W External read write status output P92 WRH DSTB External data strobe signal output P93 RD ASTB External address strobe signal output P94 HLDAK Output Bus hold acknowledge output P95 HLDRQ Input Bus hold r...

Page 35: ...connecting pins Supply external clock to X1 X2 ADTRG Input A D converter external trigger input P22 AVREF Input Reference voltage input for A D converter AVDD Positive power supply for A D converter AVSS Ground for A D converter CVDD Positive power supply for clock generator CVSS Ground for clock generator VDD Positive power supply VSS Ground VPP High voltage applying pin for program write verify ...

Page 36: ...H ASTB Hi Z Hi Z Hi Z Hi Z H H HLDRQ Operates Operates Operates HLDAK Hi Z Hi Z Hi Z L Operates Operates WAIT CLKOUT OperatesNote 2 L OperatesNote 2 OperatesNote 2 OperatesNote 2 Hi Z high impedance Retained Retains status in external bus cycle immediately before L low level output H high level output input not sampled Notes 1 Undefined immediately after the bus hold end 2 Low level output in sing...

Page 37: ...P05 Interrupt Request from Peripherals input These pins are the external interrupt request input pins 2 P10 to P17 Port 1 3 state I O These pins constitute an 8 bit I O port port 1 which can be set in the input or output mode in 1 bit units P10 to P17 function as ports as well as RPU inputs outputs and external interrupt request inputs In the operation mode port control can be selected in 1 bit un...

Page 38: ... iii ADTRG AD Trigger Input input This pin is external trigger input pin of A D converter 4 P30 to P36 Port 3 3 state I O These pins constitute an 7 bit I O port port 3 They also function as control signal pins P30 to P36 function not only as I O port pins but also as serial interface I O pins in the control mode Each bit of port 3 can be specified in the port or control mode in 1 bit units by usi...

Page 39: ...D0 to AD7 by using the MODE pin and MM register i AD0 to AD7 Address Data 0 to 7 3 state I O These pins constitute a multiplexed address data bus when the external memory is accessed They function as the A0 to A7 output pins of a 24 bit address in the address timing T1 state and as the lower 8 bit data I O bus pins of 16 bit data in the data timing T2 TW T3 The output status of these pins changes ...

Page 40: ...cified as A16 to A23 by using the MODE pin and MM register i A16 to A23 Address 16 to 23 output These pins constitute the higher 8 bits of a 24 bit address bus when the external memory is accessed The output status of these pins changes in synchronization with the rising edge of the clock in the T1 state During the idle state TI the address of the bus cycle immediately before entering the idle sta...

Page 41: ...I ii UBEN Upper Byte Enable output This is the upper byte enable signal of the 16 bit external data bus It becomes active low in byte access to an odd address It becomes inactive high in byte access to an even address This signal changes in synchronization with the rising of the clock in the T1 state of the bus cycle The status of the bus signal remains unchanged in the idle state TI Access UBEN L...

Page 42: ...ta output This is a write strobe signal output pin for the upper byte of the external 16 bit data bus x RD Read Strobe output This is a read strobe signal output pin for the external 16 bit data bus 10 P100 to P103 Port 10 3 state I O Port 10 is a 4 bit I O port that can be set in the input or output mode in 1 bit units In addition to the function as a port the pins constituting port 10 are used a...

Page 43: ...function as input and output of serial interface control signal and output of clock signal by setting of port 12 mode control register PMC12 However P126 pin functions only as a port i SO2 SO3 Serial Output 2 3 output These are serial transmit data output pins for the CSI ii SI2 SI3 Serial Input 2 3 input These are serial receive data input pins for the CSI iii SCK2 SCK3 Serial Clock 2 3 3 state I...

Page 44: ... even during reset in the ROM less mode In the single chip mode 1 the CLKOUT signal is not output until the PSC register is set low level output However in the single chip mode 2 the CKOUT signal is output 18 WAIT Wait input This control signal input pin inserts a data wait state to the bus cycle and can be activated asynchronously to CLKOUT This pin is sampled at the falling edge of the clock in ...

Page 45: ...em initialization start functions the RESET signal is also used for exiting processor power save modes HALT IDLE or STOP 21 X1 X2 Crystal input An oscillator for internal system clock generation is connected across these pins An external clock source can also be referenced by connecting the external clock input to the X1 pin and leaving the X2 pin open 22 CVDD Power Supply for Clock Generator This...

Page 46: ...age input This is a reference voltage input pin for the A D converter 29 VPP Programming Power Supply This pin supplies positive power for the PROM mode This is for µPD70F3008 or 70F3008Y 30 NC No Connection This pin is not connected internally This is for the µPD703006 703008 and 703008Y ...

Page 47: ... state Independently connect to VDD or VSS via resistor P50 AD8 to P57 AD15 P60 A16 to P67 A23 Output state Leave open P70 ANI0 to P77 ANI7 9 Connect directly to VSS P80 ANI8 to P87 ANI15 P90 LBEN WRL P91 UBEN 5 Input state Independently connect to VDD or VSS via resistor P92 R W WRH P93 DSTB RD P94 ASTB P95 HLDAK P96 HLDRQ Output state Leave open P100 PWM0 to P103 PWM3 5 Independently connect to ...

Page 48: ... with hysteresis characteristics P ch N ch VDD OUT Type 5 Type 5 K P ch N ch VDD IN OUT data output disable input enable P ch N ch VDD IN OUT data output disable input enable IN comparator VREF threshold voltage P ch N ch input enable Type 9 Type 13 G N ch IN OUT data output disable input enable 2 5 I O Circuits of Pins ...

Page 49: ...res Minimum instruction cycle 30 ns at internal 33 MHz operation Address space 16 Mbytes linear General registers Thirty two 32 bit registers Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturated operation instructions Single clock 32 bit shift instruction Long short instruction format Four types of bit manipulation instructions Set Clear Not Test ...

Page 50: ...0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Zero Register Reserved for Address Generation Interrupt Stack Pointer Stack Pointer SP Global Pointer GP Text Pointer TP Element Pointer EP Link Pointer LP PC Program Counter PSW Program Status Word ECR Exception Cause Register FEPC FEPSW Fatal Error PC Fatal Error PSW EIPC EIPSW Ex...

Page 51: ...rking register for generating immediate r2 Interrupt stack pointer Stack pointer for interrupt handler r3 Stack pointer Used to generate stack frame when function is called r4 Global pointer Used to access global variable in data area r5 Text pointer Register to indicate the start of the text areaNote r6 to r29 Address data variable registers r30 Element pointer Base pointer register when memory i...

Page 52: ...xception or interrupt occurs Because only one set of these registers is available their contents must be saved when multiple interrupts are enabled These registers save PC and PSW when NMI occurs If exception maskable interrupt or NMI occurs this register will contain information referencing the interrupt source The high order 16 bits of this register are called FECC to which exception code of NMI...

Page 53: ...cepting maskable interrupt request is disabled 4 SAT Saturated Math This flag is set if result of executing saturated operation instruction overflows if overflow does not occur value of previous operation is held 3 CY Carry This flag is set if carry or borrow occurs as result of operation if carry or borrow does not occur it is reset 2 OV Overflow This flag is set if overflow occurs during operati...

Page 54: ... branches to the reset address of external memory and instruction processing is started Instruction fetch and data access to internal ROM are disabled UBEN LBEN R W and DSTB signal are output when reset in the ROM less mode UBEN WRL WRH and RD signal are output in the ROM less mode 2 2 Flash memory programming mode µPD70F3008 70F3008Y only This mode is provided only to on chip flash memory model I...

Page 55: ...08 70F3008Y Pin Status Operation Mode VPP MODE2 MODE1 MODE0 0 V 0 0 0 ROM less mode 1 0 V 0 0 1 ROM less mode 2 0 V 0 1 0 Single chip mode 1 0 V 0 1 1 Single chip mode 2 7 8 V 1 1 1 Flash memory programming mode Other than above Setting prohibited Normal operation mode ...

Page 56: ...0H 3 4 Address Space 3 4 1 CPU address space The CPU of the V854 is of 32 bit architecture and supports up to 4 Gbytes of linear address space data space during operand addressing data access When referencing instruction addresses a linear address space program space of up to 16 Mbytes is supported Figure 3 4 shows the CPU address space Figure 3 4 CPU Address Space ...

Page 57: ...al addressing space Because the higher 8 bits of a 32 bit CPU address are ignored and the CPU address is only seen as a 24 bit external physical address the physical location XX000000H is equally referenced by multiple address values 00000000H 010000000H 02000000H through FF000000H Figure 3 5 Image on Address Space FFFFFFFFH FF000000H FEFFFFFFH Image CPU address space Image Image Image Image FE000...

Page 58: ...f the memory space are contiguous addresses is called wraparound Caution No instruction can be fetched from the 4 Kbyte area of 00FFF000H to 00FFFFFFH because this area is defined as peripheral I O area Therefore do not execute any branch operation instructions in which the destination address will reside in any part of this area 2 Data space The result of operand address calculation that exceeds ...

Page 59: ...8Y 70F3008Y only XXFFFFFFH Peripheral I O area Internal RAM area access prohibited Internal ROM area Peripheral I O area Internal RAM area External memory area Internal ROM area Peripheral I O area Internal RAM area External memory area Single chip modeNote Single chip modeNote external expansion mode ROM less mode 16 MB 1 MB 4 KB XXFFF000H XXFFEFFFH XX100000H XX0FFFFFH XX000000H XXFFE000H XXFFDFF...

Page 60: ...sical internal ROM as follows Caution Internal ROM products are µPD703008 70F3008 703008Y and 70F3008Y only Physical internal ROM 000000H to 01FFFFH 128 Kbytes The image of 000000H to 01FFFFH is seen in the rest of the area 020000H to 0FFFFFH XX0FFFFFH XX0E0000H XX0DFFFFH XX040000H XX03FFFFH XX020000H XX01FFFFH XX000000H Image Image Image Physical internal ROM Internal ROM 01FFFFH 000000H Interrup...

Page 61: ...on Table Start Address of Interrupt Exception Table Interrupt Exception Source 00000000H RESET 00000010H NMI 00000040H TRAP0n n 0 to FH 00000050H TRAP1n n 0 to FH 00000060H ILGOP 00000080H INTOV0 INTP04 INTP05 00000090H INTOV1 INTP14 000000A0H INTCC00 INTP00 000000B0H INTCC01 INTP01 000000C0H INTCC02 INTP02 000000D0H INTCC03 INTP03 000000E0H INTC10 000000F0H INTC11 00000100H INTCP12 00000110H INTC...

Page 62: ...mory area in ROM less mode or in the µPD703006 For normal operation after reset keep the destination address for the reset routine in external memory address 0 2 Internal RAM area The V854 is provided with 4 Kbytes of addresses FFE000H to FFEFFFH as a physical internal RAM area XXFFEFFFH XXFFE000H Internal RAM ...

Page 63: ...nits the higher 8 bits become undefined if the access is a read operation If a write access is made only the data in the lower 8 bits is written to the register 3 If a register with n address that can be accessed only in halfword units is accessed with a word operation the operation is replaced with two halfword operations The first operation lower 16 bits accesses to the register with n address a...

Page 64: ...ernal expansion mode is specified The same image as that of the physical external memory can be seen continuously on the external memory area as shown in Figure 3 6 when the memory is not fully expanded to 16 Mbytes The internal RAM area peripheral I O area and internal ROM area in single chip mode are not subject to external memory access Figure 3 6 External Memory Area when expanded to 64 K 256 ...

Page 65: ...expanded to 4 Mbytes Note The image of the physical external memory can be seen continuously in the ROM less mode or with the µPD703006 XXFFFFFFH XX000000H Physical external memory 3FFFFFH 000000H Peripheral I O Internal RAM Image Image Image Internal ROMNote XXFFDFFFH XX100000H External memory ...

Page 66: ...NCTIONS Figure 3 8 External Memory Area when fully expanded Note This area becomes an external memory area in the ROM less mode or with the µPD703006 XXFFFFFFH Peripheral I O XX100000H XX000000H XXFFDFFFH Internal RAM External memory Internal ROMNote ...

Page 67: ...ode register MM The MODEn pins specify the operation mode of the V854 For specifying refer to 3 3 2 Specifying operation mode In ROM less mode the pins of port 4 to port 6 and P90 to P94 become the control mode during reset thereby the external memory can be used In single chip mode the port control mode alternate pins become the port mode thereby the external memory cannot be used When the extern...

Page 68: ...ever bits 4 to 7 are fixed to 0 Bit Position Bit Name Function 3 MM3 Memory Expansion Mode Specifies operation mode of P95 and P96 of port 9 MM3 Operation Mode P95 P96 0 Port mode Port 1 External expansion mode HLDAK HLDRQ 2 to 0 MM2 to MM0 Memory Expansion Mode Specifies operation mode of ports 4 5 6 and 9 P90 to P94 MM2 MM1 MM0 Address Port 4 Port 5 Port 6 Port 9 Space P90 to P94 0 0 0 Port mode...

Page 69: ...e starting from address 00000000H unconditionally corresponds to the memory map of the program space 2 Data space For the efficient use of resources to be performed through the wrap around feature of the data space the continuous 8 Mbyte address spaces 00000000H to 007FFFFFH and FF800000H to FFFFFFFFH of the 4 Gbyte CPU are used as the data space With the V854 16 Mbyte physical address space is se...

Page 70: ...2H FFFFF3D1H 00000000H 16 MB 8 MB Internal ROM Internal ROM External memory Internal RAM Peripheral I ONote Program space Data space Peripheral I O Internal RAM External memory Peripheral I O Internal RAM External memory External memory Internal ROM XXFFFFFFH XXFFF3D2H XXFFF3D1H XXFFF000H XXFFEFFFH XXFFE000H XXFFDFFFH XX100000H XX0FFFFFH XX020000H XX01FFFFH XX800000H XX7FFFFFH XX000000H FFFFF000H ...

Page 71: ...PM3 FFFFF028H Port 4 mode register PM4 FFFFF02AH Port 5 mode register PM5 FFFFF02CH Port 6 mode register PM6 FFFFF032H Port 9 mode register PM9 FFFFF034H Port 10 mode register PM10 FFFFF036H Port 11 mode register PM11 FFFFF038H Port 12 mode register PM12 FFFFF03AH Port 13 mode register PM13 FFFFF03CH Port 14 mode register PM14 FFFFF040H Port 0 mode control register PMC0 00H FFFFF042H Port 1 mode c...

Page 72: ...ator prescaler mode register 2 BPRM2 00H FFFFF0A8H Clocked serial interface mode register 2 CSIM2 FFFFF0AAH Serial I O shift register 2 SIO2 Undefined FFFFF0B4H Baud rate generator register 3 BRGC3 FFFFF0B6H Baud rate generator prescaler mode register BPRM3 00H FFFFF0B8H Clocked serial interface mode register 3 CSIM3 FFFFF0BAH Serial I O shift register 3 SIO3 Undefined FFFFF0C0H Asynchronous seria...

Page 73: ...upt control register CSIC0 FFFFF126H Interrupt control register CSIC1 FFFFF128H Interrupt control register CSIC2 FFFFF12AH Interrupt control register CSIC3 FFFFF12CH Interrupt control register IIIC0 FFFFF12EH Interrupt control register SEIC0 FFFFF130H Interrupt control register SRIC0 FFFFF132H Interrupt control register STIC0 FFFFF134H Interrupt control register ADIC0 FFFFF136H Interrupt control r...

Page 74: ...register 01 CC01 FFFFF25CH Capture compare register 02 CC02 FFFFF260H Capture compare register 03 CC03 FFFFF264H Timer 0L TM0L R 0000H FFFFF266H Capture compare register 00L CC00L R W Undefined FFFFF268H Capture compare register 01L CC01L FFFFF26AH Capture compare register 02L CC02L FFFFF26CH Capture compare register 03L CC03L FFFFF270H Timer control register 1 TMC1 01H FFFFF274H Timer 1 TM1 R 000...

Page 75: ... R W Undefined FFFFF354H Capture register 3 CP3 R FFFFF360H PWM control register 3 PWMC0 R W 05H FFFFF362H PWM modulo register 0 PWM0 Undefined FFFFF364H PWM prescaler register 0 PWPR0 00H FFFFF368H PWM control register 1 PWMC1 05H FFFFF36AH PWM modulo register 1 PWM1 Undefined FFFFF36CH PWM prescaler register 1 PWPR1 00H FFFFF370H PWM control register 2 PWMC2 05H FFFFF372H PWM modulo register 2 P...

Page 76: ...ts 16 bits 32bits FFFFF39EH A D conversion result register 7 ADCR7 R Undefined FFFFF3C0H Port 13 buffer register PB R W FFFFF3C2H Output latch RTP FFFFF3D0H Clock output mode register CL0M 00H Bit Units for Manipulation Address Function Register Name Symbol R W After Reset ...

Page 77: ... an interrupt request is accepted between the time PRCMD is issued 2 and the specific register write operation 3 that follows immediately after the write operation to the specific register is not performed and a protection error PRERR bit of SYS register is 1 may occur Therefore set the NP bit of PSW to 1 1 to disable the acceptance of INT NMI The above also applies when a bit manipulation instruc...

Page 78: ...cessing the special register to prevent incorrect writing to the special registers due to the erroneous program execution This register can be read written in 8 bit units It becomes undefined values in a read cycle Occurrence of illegal store operations can be checked by the PRERR bit of the SYS register Bit Position Bit Name Function 7 to 0 REG7 to Registration Code REG0 Specific Register Registr...

Page 79: ... occurs 0 UNLOCK Unlock Status Flag Read only flag Indicates the PLL unlock state For details refer to 6 4 PLL Stabilization 0 Locked 1 Unlocked Operation conditions of PRERR Flag Set conditions 1 If the store instruction most recently executed to peripheral I O does not write PRERR 1 data to the PRCMD register but to the specific register 2 If the first store instruction executed after the write ...

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Page 81: ...s such as ROM and RAM and I O can be connected 4 1 Features 16 bit data bus Can be connected to external devices with pins having alternate function as port Wait function Programmable wait function of up to 3 states per 2 blocks External wait function through WAIT pin Idle state insertion function Bus mastership arbitration function Bus hold function ...

Page 82: ...ansion mode register MM In ROM less mode the bus interface function of each pin is unconditionally enabled by the MODE input n 0 to 2 For the details of specifying an operation mode of the external bus interface refer to 3 4 6 1 Memory expansion mode register MM 4 2 2 Control register 1 System control register SYC This register switches control signals for bus interface The system control register...

Page 83: ...f basic clocks necessary for accessing each resource is as follows Resource bus width Bus Cycle Type Internal ROM Internal RAM Internal Peripheral External Memory 32 bits 32 bits I O 16 bits 16 bits Instruction fetch 1 3 Disabled 3 n Operand data access 3 1 3 n 3 n Remarks 1 Unit clock access 2 n number of wait insertions ...

Page 84: ...o types the access to even address and the access to odd address 2 Halfword access 16 bits In halfword access to external memory data is dealt with as it is because the data bus is fixed to 16 bits 3 Word access 32 bits In word access to external memory lower halfword is accessed first and then the upper halfword is accessed 0 7 0 7 8 15 Byte data External data bus a Access to even address 0 0 15 ...

Page 85: ...rea becomes the external memory area Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 Peripheral I O area Internal RAM area FFFFFFH FFF000H FFEFFFH FFE000H External memory area FFFFFFH F00000H EFFFFFH E00000H DFFFFFH D00000H CFFFFFH C00000H BFFFFFH B00000H AFFFFFH A00000H 9FFFFFH 900000H 8FFFFFH 800000H 7FFFFFH 70...

Page 86: ...Number of wait states to be inserted 0 0 0 0 1 1 1 0 2 1 1 3 n Blocks into which wait states are inserted 0 Blocks 0 1 1 Blocks 2 3 2 Blocks 4 5 3 Blocks 6 7 4 Blocks 8 9 5 Blocks 10 11 6 Blocks 12 13 7 Blocks 14 15 Cautions 1 Block 0 is reserved for the internal ROM area in the single chip mode It is not subject to programmable wait control regardless of the setting of DWC and is always accessed ...

Page 87: ...not satisfied the wait state may or may not be inserted in the next state 4 5 3 Relations between programmable wait and external wait A wait cycle is inserted as a result of an OR operation between the wait cycle specified by the set value of programmable wait and the wait cycle controlled by the WAIT pin In other words the number of wait cycles is determined by the programmable wait value or the ...

Page 88: ...e read written in 16 bit units Bit Position Bit Name Function 15 13 11 BCn1 Bus Cycle 9 7 5 3 1 n 0 to 7 Specifies insertion of idle state 0 Not inserted 1 Inserted n Blocks into Which Idle State Is Inserted 0 Blocks 0 1 1 Blocks 2 3 2 Blocks 4 5 3 Blocks 6 7 4 Blocks 8 9 5 Blocks 10 11 6 Blocks 12 13 7 Blocks 14 15 Cautions 1 Block 0 is reserved for the internal ROM area in the single chip mode t...

Page 89: ...n is used and when a DMA controller is connected Bus hold request is not acknowledged between the first and the second word access Bus hold request is also acknowledged between read access and write access in read modify write access of bit manipulation instruction 4 7 2 Bus hold procedure The procedure of the bus hold function is illustrated below 1 HLDRQ 0 accepted 2 All bus cycle start request ...

Page 90: ... Timing 1 Memory read 0 wait Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The dotted line indicates the high impedance state T1 T2 T3 CLKOUT A16 to A23 AD0 to AD15 Address Data Address ASTB R W DSTB RD UBEN LBEN WAIT WRL WRH H ...

Page 91: ... Memory read 1 wait Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The dotted line indicates the high impedance state T1 T2 TW CLKOUT A16 to A23 AD0 to AD15 Address Address ASTB R W DSTB RD UBEN LBEN WAIT WRL WRH T3 Data H ...

Page 92: ...y read 0 wait idle state Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The dotted line indicates the high impedance state T1 T2 T3 CLKOUT A16 to A23 AD0 to AD15 Address Address ASTB R W DSTB RD UBEN LBEN WAIT WRL WRH H TI Data ...

Page 93: ... read 1 wait idle state Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The dotted line indicates the high impedance state T1 T2 TW CLKOUT A16 to A23 AD0 to AD15 Address Address ASTB R W DSTB RD UBEN LBEN WAIT WRL WRH T3 Data TI H ...

Page 94: ...yte data is accessed AD8 to AD15 output invalid data when even address byte data is accessed Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The dotted line indicates the high impedance state T1 T2 T3 CLKOUT A16 to A23 AD0 to AD15 Address DataNote Address ASTB R W DSTB UBEN LBEN WAIT RD WRL WRH H ...

Page 95: ...te data is accessed AD8 to AD15 output invalid data when even address byte data is accessed Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The dotted line indicates the high impedance state T1 T2 TW CLKOUT A16 to A23 AD0 to AD15 Address ASTB R W DSTB UBEN LBEN WAIT RD WRL WRH T3 DataNote Address H ...

Page 96: ...Caution When the bus hold state is entered after the write cycle a high level signal may be briefly output from the R W pin immediately before the HLDAK signal changes from the high level to the low level CLKOUT R W DSTB RD WRL WRH UBEN LBEN WAIT HLDRQ T2 T3 TH TH TH TH TI T1 HLDAK A16 to A23 AD0 to AD15 Address Address Data Address ASTB Undefined Undefined Undefined Address ...

Page 97: ...on fetch continuous 4 4 10 Memory Boundary Operation Condition 4 10 1 Program space 1 Do not execute branch to the peripheral I O area or continuous fetch from the internal RAM area to peripheral I O area Of course it is impossible to fetch from external memory If branch or instruction fetch is executed nevertheless the NOP instruction code is continuously fetched 2 A prefetch operation straddling...

Page 98: ...when accessing to certain timer counter registers wait may take place from 3 to 4 cycles Peripheral I O Register Access Number of Waits Number of Cycles CC00 to CC03 Read 2 8 Write 0 2 6 8 CC00L to CC03L CC3 Read 1 4 Write 0 1 3 4 CP10 to CP13 CM10 Read 2 8 CM11 TM0 TM1 Write 0 6 CP10L CP13L CM10L CM11L Read 1 4 TM0L TM1L CP3 TM3 Write 0 3 CM20 to CM24 Read 0 1 6 8 Write 0 1 6 8 TM20 to TM24 Read ...

Page 99: ...ernal peripheral hardware and external sources Moreover exception processing can be started by the TRAP instruction software exception or by generation of an exception event fetching of an illegal op code 5 1 Features Interrupt Non maskable interrupt 1 source Maskable interrupt 31 sources 8 levels programmable priorities control Multiple interrupt control according to priority Mask specification f...

Page 100: ...t INTCP13 P1IC3 INTP12 INTP13 input Pin 9 0110H 00000110H nextPC Interrupt INTCM10 CM1IC0 CM10 coincidence RPU 10 0120H 00000120H nextPC Interrupt INTCM11 CM1IC1 CM11 coincidence RPU 11 0130H 00000130H nextPC Interrupt INTP20 CM2IC0 INTP20 CM20 Pin RPU 12 0140H 00000140H nextPC INTCM20 coincidence Interrupt INTP21 CM2IC1 INTP21 CM21 Pin RPU 13 0150H 00000150H nextPC INTCM21 coincidence Interrupt I...

Page 101: ...IC0 UART reception UART 24 0200H 00000200H nextPC completion Interrupt INTST STIC0 UART transmission UART 25 0210H 00000210H nextPC completion Interrupt INTAD ADIC0 A D conversion end ADC 26 0220H 00000220H nextPC Interrupt INTP50 P5IC0 INTP50 input Pin 27 0230H 00000230H nextPC Interrupt INTP51 P5IC1 INTP51 input Pin 28 0240H 00000240H nextPC Interrupt INTP52 P5IC2 INTP52 input Pin 29 0250H 00000...

Page 102: ...after the original service routine of the non maskable interrupt under execution has been terminated by the RETI instruction or when PSW NP is cleared to 0 by the LDSR instruction Note that if two or more NMI requests are input during the execution of the service routine for an NMI the number of NMIs that will be acknowledged after PSW NP goes to 0 is only one The operation at the execution of pen...

Page 103: ...ode 0010H to the higher half word FECC of ECR 4 Sets the NP and ID bits of PSW and clears the EP bit 5 Loads the handler address 00000010H of the non maskable interrupt routine to the PC and transfers control Figure 5 1 illustrates how the non maskable interrupt is processed Figure 5 1 Non Maskable Interrupt Processing NMI input Non maskable interrupt request Interrupt processing Interrupt request...

Page 104: ...quest is generated twice while an NMI service routine is executing Main routine NMI request NMI request PSW NP 1 NMI request pending because PSW NP 1 Pending NMI request processed Main routine NMI request NMI request Kept pending because NMI service program is being processed Kept pending because NMI service program is being processed NMI request Only one NMI request is accepted even though two or...

Page 105: ...Transfers control back to the restored PC address and PSW status Figure 5 3 illustrates how the RETI instruction is processed Figure 5 3 RETI Instruction Processing Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during the non maskable interrupt process in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set PSW EP...

Page 106: ... is 60 to 220 ns The signal input that changes in less than this time period is not internally acknowledged NMI pin is used for canceling the software stop mode In the software stop mode noise elimination does not use system clock for noise elimination because the internal system clock is stopped 5 2 5 Edge detection function of NMI pin INTM0 is a register that specifies the valid edge of the non ...

Page 107: ...upt request has been acknowledged the acceptance of other maskable interrupts is disabled and the interrupt disabled DI status is set When the EI instruction is executed in an interrupt processing routine the interrupt enabled EI status is set which enables interrupts having a higher priority to immediately interrupt the current service routine in progress Note that only interrupts with a higher p...

Page 108: ...NTP10 Edge detection Noise elimination INTP13 Edge detection 1 to 128 frequency division Noise elimination INTP11 Edge detection RPU 1 to 64 frequency division Noise elimination INTP12 Edge detection 1 to 64 frequency division Selector Noise elimination INTP30 Edge detection Noise elimination Edge detection Noise elimination Edge detection Noise elimination Edge detection Noise elimination Edge de...

Page 109: ...rocessing and transfers control to a handler routine 1 Saves the restored PC to EIPC 2 Saves the current PSW to EIPSW 3 Writes an exception code to the lower half word of ECR EICC 4 Sets the ID bit of PSW and clears the EP bit 5 Loads the corresponding handler address to the PC and transfers control Figure 5 5 illustrates how the maskable interrupts are processed ...

Page 110: ...ETI and LDSR instructions the pending INT input starts the new maskable interrupt processing Maskable interrupt request Interrupt processing EIPC EIPSW ECR EICC PSW EP PSW ID PC INTC accepted CPU processing XXIF 1 No Yes XXMK 0 Priority higher than that of interrupt currently processed Interrupt request pending PSW NP PSW ID Interrupt process pending No No No No 1 0 1 0 Interrupt request INT input...

Page 111: ...rs control to the restored PC address and PSW status Figure 5 6 illustrates the processing of the RETI instruction Figure 5 6 RETI Instruction Processing Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the maskable interrupt process in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set PSW EP back to 0 ...

Page 112: ... control based on default priority levels services them in the order of the priority level allocated to each interrupt request type default priority level beforehand For more information refer to Table 5 1 The programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag The relation between the programmable priority levels and defau...

Page 113: ... b level 2 Processing of c Interrupt request c level 3 Interrupt request d level 2 Processing of d Processing of e EI Interrupt request e level 2 Interrupt request f level 3 Processing of f EI Processing of g Interrupt request g level 1 Interrupt request h level 1 Processing of h Interrupt request h is kept pending even if interrupts are enabled because its priority is the same as that of g Interr...

Page 114: ...0 Interrupt request u level 2 Note 2 Interrupt request t level 2 Note 1 Processing of p Processing of q Processing of r EI If levels 3 to 0 are accepted Interrupt request j is kept pending because its priority is lower than that of i k that occurs after j is accepted because it has the higher priority Interrupt requests m and n are kept pending because processing of l is performed in the interrupt...

Page 115: ...pt request a level 2 Interrupt request b level 1 Interrupt request c level 1 Default priority a b c Processing of interrupt request b Processing of interrupt request c Processing of interrupt request a Interrupt request b and c are accepted first according to their priorities Because the priorities of b and c are the same b is accepted first because it has the higher default priority ...

Page 116: ...nterrupt request is accepted 6 xxMKn Mask Flag Interrupt mask flag 0 Enables interrupt processing 1 Disables interrupt processing pending 2 to 0 xxPRn2 to xxPRn0 Priority Specifies eight levels of priorities for each interrupt xxPRn2 xxPRn1 xxPRn0 Interrupt priority specification bit 0 0 0 Specifies level 0 highest 0 0 1 Specifies level 1 0 1 0 Specifies level 2 0 1 1 Specifies level 3 1 0 0 Speci...

Page 117: ...0 FFFFF118H CM2IC0 CM2IF0 CM2MK0 0 0 0 CM2PR02 CM2PR01 CM2PR00 FFFFF11AH CM2IC1 CM2IF1 CM2MK1 0 0 0 CM2PR12 CM2PR11 CM2PR10 FFFFF11CH CM2IC2 CM2IF2 CM2MK2 0 0 0 CM2PR22 CM2PR21 CM2PR20 FFFFF11EH CM2IC3 CM2IF3 CM2MK3 0 0 0 CM2PR32 CM2PR31 CM2PR30 FFFFF120H CM2IC4 CM2IF4 CM2MK4 0 0 0 CM2PR42 CM2PR41 CM2PR40 FFFFF122H CC3IC0 CC3IF0 CC3MK0 0 0 0 CC3PR02 CC3PR01 CC3PR00 FFFFF124H CSIC0 CSIF0 CSMK0 0 0 ...

Page 118: ... n accepted Remark n 0 to 7 priority level 5 3 6 Maskable interrupt status flag ID The interrupt disable status flag ID of the PSW controls the enabling and disabling of maskable interrupt requests Bit Position Bit Name Function 5 ID Interrupt Disable Indicates enabling disabling of maskable interrupt processing 0 Maskable interrupt accepting enabled 1 Maskable interrupt accepting disabled pending...

Page 119: ...64 φ 128 or φ 256 For the settings write values to INTM7 register refer to 5 3 8 2 a External interrupt request register 7 INTM7 Pin fSMP Noise Elimination Time INTP00 to INTP03 φ 2 to 3 system clocks TCLR0 INTP04 φ TI0 INTP05 φ INTP10 to INTP13 φ TI1 INTP14 φ TI20 INTP20 to TI24 INTP24 φ ADTRG φ INTP30 φ 2 to 3 system clocks φ 64 128 to 192 system clocks φ 128 256 to 384 system clocks φ 256 512 t...

Page 120: ...uch cases attach a filter to the input pin to eliminate the noise 5 3 8 Edge detection function 1 Edge detection of INTP pin except INTP30 pin TI pin TCLR pin ADTRG pin These pins can be programmably selected The valid edge can be selected from the followings Rising edge Falling edge Both rising and falling edges The detected INTP signal becomes an interrupt source or capture trigger The block dia...

Page 121: ...o 53 20 to 24 ESn1 ESn0 Operation 50 to 53 0 0 Falling edge AD 0 1 Rising edge 1 0 RFU reserved 1 1 Both rising and falling edges Address FFFFF182H 7 ES031 INTP03 INTP02 INTP01 INTP00 INTM1 Control pin 6 ES030 5 ES021 4 ES020 3 ES011 2 ES010 1 ES001 0 ES000 After reset 00H FFFFF184H INTM2 00H FFFFF186H INTM3 00H FFFFF188H INTM4 00H ES241 ES240 ES231 ES230 ES221 ES220 ES211 ES210 ES111 ES110 ES101 ...

Page 122: ...es The edge detected INTP30 signal becomes the capture trigger of CC3 register and CP3 register of timer function The triggers of CC3 register and CP3 register have reverse edges However when both edges are specified either one trigger is valid The block diagram of the edge detection of INTP30 pin is shown below INTP30 φ φ φ φ Noise elimination fSMP Rising edge detection CC3 capture trigger ES300 ...

Page 123: ...INTP30 CC3 Capture Trigger CP3 Capture Trigger 0 0 Falling edge Rising edge 0 1 Rising edge Falling edge 1 0 Without selection edge Both rising and falling edges 1 1 Both rising and falling edges Not captured Remark φ internal system clock 1 0 SCS1 SCS0 Sampling Clock Select Specifies sampling clock SCS1 SCS0 Sampling Clock Pulse Width Eliminated Minimum Pulse Width fSMP as Noise Recognized as Sig...

Page 124: ...ow The block diagram of the frequency divider is shown below Remark n 0 to 2 1 Event divide counter 0 to 2 EDV0 to EDV2 This register counts the valid edge of the INTPn input signal n 11 to 13 The EDV0 and EDV1 registers are configured with a 6 bit counter and EDV2 register is configured with a 7 bit counter These registers are cleared at the following timings Coincidence of the value in the event...

Page 125: ...ster EVS This register selects the signal to be input to EDV2 register This register can be read written in 8 or 1 bit units Bit Position Bit Name Function 0 ESE Event Select Selects input signal to EDV2 register 0 INTP13 signal 1 INTP12 signal frequency division result by EDVC1 register Address 7 0 EDV0 6 0 5 4 3 2 1 0 After reset 00H FFFFF1B8H FFFFF1B6H EDV1 00H 0 0 FFFFF1BAH EDV2 00H 0 EDV05 ED...

Page 126: ...CR interrupt source 4 Sets the EP and ID bits of PSW 5 Loads the handler address 00000040H or 00000050H of the software exception routine in the PC and transfers control Figure 5 10 illustrates how a software exception is processed Figure 5 10 Software Exception Processing Note TRAP instruction format TRAP vector where vector is 0 to 1FH The handler address is determined by the operand of the TRAP...

Page 127: ...sfers control to the restored PC address and PSW status Figure 5 11 illustrates the processing of the RETI instruction Figure 5 11 RETI Instruction Processing Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the software exception process in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set PSW EP back ...

Page 128: ...to indicate that trap processing is in progress It is set when a trap occurs Bit Position Bit Name Function 6 EP Exception Pending Indicates that trap processing is in progress 0 Trap processing not in progress 1 Trap processing in progress 31 0 PSW After reset 00000020H 7 NP 6 EP 5 ID 4 SAT 3 CY 2 OV 1 S Z 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 129: ...legal op code not be defined since an instruction may newly be assigned later 5 5 2 Operation If an exception trap occurs the CPU performs the following processing and transfers control to the handler routine 1 Saves the restored PC to EIPC 2 Saves the current PSW to EIPSW 3 Writes an exception code 0060H to the lower 16 bits EICC of ECR 4 Sets the EP and ID bits of PSW 5 Loads the handler address...

Page 130: ...control to the restored PC address and PSW status Figure 5 13 illustrates the processing of the RETI instruction Figure 5 13 RETI Instruction Processing Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the exception trap process in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set PSW EP back to 1 using...

Page 131: ... routine is completed If an interrupt with a lower or equal priority is generated and a service routine is currently in progress the later interrupt will be pended Multiple processing control of maskable interrupts is performed when in the state of interrupt acceptance ID 0 To perform maskable interrupt even in an interrupt processing routine this control must be set in the state of acceptance ID ...

Page 132: ...est for multiple interrupt processing control To set a priority level write values to the xxPRn0 to xxPRn2 bits of the interrupt request control register xxICn corresponding to each maskable interrupt request At system reset the interrupt request is masked by the xxMKn bit and the priority level is set to 7 by the xxPRn0 to xxPRn2 bits The priorities of maskable interrupts are as follows High Leve...

Page 133: ...ss to interrupt control register 5 8 Periods Where Interrupt is Not Acknowledged An interrupt request is acknowledged while an instruction is being executed However no interrupt request will be acknowledged between an interrupt request non sample instruction and the next instruction EI instruction DI instruction LDSR reg2 0x5 instruction vs PSW In the following conditions an interrupt may not be a...

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Page 135: ... by PLL Phase Locked Loop synthesizer Clock source Oscillation through oscillator connection fXX φ φ 5 External clock input fXX φ 2 φ φ 5 Power save control HALT mode IDLE mode Software STOP mode Clock output inhibit function Internal system clock output function 6 2 Configuration Remark φ Internal system clock fTBC Time base counter TBC input clock fXX 2 x1 fXX x2 CKSEL PLLSEL Clock Generator TBC...

Page 136: ... the external clock frequency fXX is 32 MHz internal system clock φ 16 MHz or more 6 3 2 PLL mode In the PLL mode an external clock is input by connecting an external oscillator which is multiplied by the PLL synthesizer to generate the internal system clock φ The PLL multiplication number that can be selected is either one or five The PLL multiplication number can be selected by the PLLSEL pin re...

Page 137: ...ntents are not written by mistake due to erroneous program execution This register can be read written in 8 or 1 bit units Bit Position Bit Name Function 1 0 CKDIV1 Clock Divide CKDIV0 Sets the internal system clock frequency in the PLL mode Operation Mode Pins CKC Internal System CKSEL PLLSEL CKDIV1 CKDIV0 Clock φ Direct mode H Note 0 0 fXX 2 H Note Any values 1 Setting prohibited H Note 1 Any va...

Page 138: ...1 Example of settings The example of settings is as below Operation Mode Pins CKC Register Input Clock Internal System CKSEL PLLSEL CKDIV1 CKDIV0 fXX Clock φ Direct mode H Note 0 0 16 MHz 8 MHz PLL mode 1 x L L 0 0 33 MHz 33 MHz multiplication L L 1 0 33 MHz 6 6 MHz L L 1 1 33 MHz 3 3 MHz PLL mode 5 x L H 0 0 6 6 MHz 33 MHz multiplication L H 1 0 6 6 MHz 6 6 MHz L H 1 1 6 6 MHz 3 3 MHz Other than ...

Page 139: ...is is a read only flag and indicates unlock status of PLL It holds 0 as long as lock up status is maintained and is not changed even if system is reset 0 Indicates lock status 1 Indicates unlock status Remark For the description of the PRERR flag refer to 3 4 9 2 System status register SYS If the unlock status condition should arise due to a power or clock source failure the UNLOCK flag should be ...

Page 140: ...he V854 to the IDLE mode The IDLE mode is somewhere between the STOP and HALT modes in terms of clock stabilization time and power consumption and is used in applications where the clock oscillation time should be eliminated but low power consumption is required Caution When inputting external clocks continue the supply of clocks 3 Software STOP mode In this mode the CPU clock the internal system ...

Page 141: ...trol PLL mode Oscillation by Normal crystal oscillator HALT x IDLE x x STOP x x x x External clock Normal x HALT x x IDLE x x x STOP x x x x Direct mode Normal x x HALT x x x IDLE x x x x STOP x x x x Operates x Stops Status Transition Diagram Clock Source Standby Mode Oscillator Circuit OSC Clock Supply to Peripheral I O Clock Supply to CPU PLL Synthesizer Normal Software STOP Released by RESET o...

Page 142: ...ecifies oscillation stabilization time 0 215 fTBC s 1 216 fTBC s For details refer to explanation of Time base counter TBC in section 6 6 Specifying Oscillation Stabilization Time 4 CESEL Crystal External Select Specifies functions of X1 and X2 pins 0 Oscillator connected to X1 and X2 pins 1 External clock connected to X1 pin When CESEL 1 the software STOP mode cannot be used 2 IDLE IDLE Mode Spec...

Page 143: ...CPU continue to operate Table 6 2 shows the status of each hardware unit in the HALT mode Table 6 2 Operating Status in HALT Mode Function Operating Status Clock Generator Operates Internal System Clock Operates CPU Stops I O Port Retained Peripheral Function Operates Internal Data Status of internal data before setting of HALT mode such as CPU registers status data and internal RAM contents are r...

Page 144: ...nterrupt request under execution is generated the HALT mode is released but the newly generated interrupt request is not accepted The new interrupt request will be kept pending ii If an interrupt request with a priority higher including NMI request than the interrupt request under execution is generated the HALT mode is released and the interrupt request is also accepted Operation after HALT mode ...

Page 145: ...egisters and internal RAM immediately before entering the IDLE mode are retained The on chip peripheral functions are stopped in this mode External bus hold request HLDRQ is not accepted Table 6 3 shows the hardware status in the IDLE mode Table 6 3 Operating Status in IDLE Mode Function Operating Status Clock Generator Operates Internal System Clock Stops CPU Stops I O Port Retained Peripheral Fu...

Page 146: ...rupt processing that is started by the NMI signal input when the IDLE mode is released is treated in the same manner as a normal NMI interrupt that is processed because there is only one vector address of the NMI interrupt Therefore if it is necessary to distinguish between the two types of NMI interrupts a software flag should be defined in advance and the flag must be set before setting the IDLE...

Page 147: ...nts of the registers and internal RAM immediately before entering the STOP mode are retained The on chip peripheral function also stops operation Table 6 4 shows the hardware status in the software STOP mode Table 6 4 Operating Status in Software STOP Mode Function Operating Status Clock Generator Stops Internal System Clock Stops CPU Stops I O PortNote 1 Retained Peripheral Function Stops Interna...

Page 148: ... the STOP mode is released and the interrupt is not accepted The interrupt request is retained and kept pending NMI interrupt processing on releasing STOP mode The interrupt processing that is started by the NMI signal input when the STOP mode is released is treated in the same manner as a normal NMI interrupt that is processed because there is only one handler address of the NMI interrupt Therefo...

Page 149: ... level width after valid edge of NMI input has been detected Count time of TBC After a specific time has elapsed the system clock output is started and execution branches to the handler address of the NMI interrupt During inactivity the NMI pin should be kept at the inactive level e g when the valid edge is specified to be the falling edge If an operation to enter the STOP mode is performed while ...

Page 150: ... system is reset Time base counter TBC The time base counter TBC is used to secure the oscillation stabilization time of the oscillator circuit when the software STOP mode is released In oscillator connecting mode CESEL 0 TBC counts the oscillation stabilization time after the STOP mode is released and the execution of a program is started after the counting is completed In both the PLL mode CKSEL...

Page 151: ...nt Time TBCS Frequency Division Count Time fXX 5 0 MHz fXX 6 6 MHz fXX 25 0 MHz fXX 33 0 MHz 0 215 fTBC 13 1 ms 9 8 ms 2 6 ms 2 0 ms 1 216 fTBC 26 2 ms 19 6 ms 5 2 ms 4 0 ms fTBC fXX 2 Figure 6 1 Block Configuration TBC 15 16 bits CG Overflow fTBC Oscillation stabilization time control circuit ...

Page 152: ...on mode in combination with the HALT IDLE or software STOP mode the power dissipation can be effectively reduced for how to write these bits refer to 6 5 2 Control registers Clock output inhibit mode The clock output from the CLKOUT pin is inhibited This mode is ideal for single chip mode systems or systems that fetch instructions to external expansion devices or asynchronously accesses data Becau...

Page 153: ... low level output In the PROM mode the CLKOUT signal is not output low level output 6 7 3 CLO signal output control The clock to be output to CLO pin can be selected by the FS bit of the CLOM register CLO pin outputs a signal which has the same level as that of the LV bit when the CLE bit is 0 Signal is output synchronized with the clock the frequency selected by the FS bit immediately after the C...

Page 154: ...ncy Select FS0 Selects the frequency of CLO signal FS2 FS1 FS0 Selection of Frequency 0 0 0 φ 0 0 1 φ 2 0 1 0 φ 4 0 1 1 φ 8 1 0 0 φ 16 Others Setting prohibited Remark φ Internal system clock Caution Do not change the values of the other bits LV FS2 to FS0 during setting of the CLE bit 1 Do not change the values of other bits LV FS2 to FS0 simultaneously with changing the value of the CLE bit 2 1 ...

Page 155: ...es to be output while clock is being output When clock output is disabled the signal of the same level that of the LV bit before HALT mode is set is output b Software STOP mode IDLE mode Disables clock output before setting these modes the CLE bit is cleared by software The signal of the same level as that of the LV bit before these modes are set is output from the CLO pin ...

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Page 157: ...64 1 to 128 frequency divider Can be used as a trigger of real time output port CM10 coincidence Overflow interrupt request and overflow flag Clearing and starting timer Applications measurement of pulse interval and frequency of software servo etc Timer 2 16 bit interval timer counter 5 channels Compare registers 1 Toggle output 1 External input pulse measurement Clearing and starting timer Appli...

Page 158: ...0 INTP10 CP11 INTCP11 Frequency division of INTP11 CP12 INTCP12 Frequency division of INTP12 CP13 INTCP13 Frequency division of INTP12 INTP13 CM10 R W INTCM10 Real time output port CM11 INTCM11 Timer 2 16 TM20 R INTCM2n input CM20 R W Software clear INTCM20 TO20 T TM21 R CM21 R W INTCM21 TO21 T TM22 R CM22 R W INTCM22 TO22 T TM23 R CM23 R W INTCM23 TO23 T TM24 R CM24 R W INTCM24 TO24 T Timer 3 16 ...

Page 159: ...NTCC03 INTP03 S OVF0 RNote Q Q TM0 24 2 4 256 INTOV0 INTP04 INTP05 TCLR0 INTP04 TI0 INTP05 Edge detection Clear and count control Edge detection Noise elimination Noise elimination φ φ φ Selector Selector Selector Selector Selector Selector INTP10 INTP11 INTP12 INTP13 TI1 INTP14 Edge detection Edge detection frequency division Edge detection Edge detection Noise elimination Noise elimination Noise...

Page 160: ... Timer 3 16 bit interval timer Remark φ Internal system clock TI2n INTP2n OVF2n T Q TM2n 16 CM2n 16 2 4 256 INTCM2n INTP2n TO2n Edge detection Noise elimination φ φ φ Selector Selector CS2 Clear start control Edge detection Edge detection Noise elimination CC3 16 CP3 16 INTP30 INTCC3 OVF3 TM3 16 2 4 256 φ φ φ Selector 64 128 256 φ φ φ φ Selector CS3 Clear start control ...

Page 161: ...e high order 8 bits are fixed to 0 and are ignored during write operation and 16 bit read write access is enabled for CC0nL To access the low order 24 bits or the low order 16 bits of these registers specify CC0n and CC0nL respectively Remark n 0 to 3 a When used as a capture register When a capture compare register is used as a capture register it detects the valid edge of the corresponding exter...

Page 162: ...nt clock The timer is started or stopped by the CE1 bit of timer control register 1 TMC1 2 Capture registers 10 to 13 CP10 to CP13 CP10L to CP13L The capture registers are 24 bit registers connected to TM1 These registers can be only read in 32 bit units CP1n is specified in 32 bit access to this register CP1nL is specified in lower 16 bit access Only 32 bit read access is enabled for CP1n and onl...

Page 163: ...1n is specified in 32 bit access to this register CM1nL is specified in lower 16 bit access CM1n can be read or written in 32 bit units The values written in bits 24 to 31 are ignored CM1nL can be read or written in 16 bit units 00H is written in the higher bits bits 16 to 23 in write access to CM1nL Remark n 0 1 31 24 23 CM1n Addresses FFFFF278H FFFFF27CH Addresses FFFFF292H FFFFF294H 00000000 Af...

Page 164: ...e of the timer coincides with the value of the compare register CM2n the timer is cleared by the next clock tick If the division ratio is large and results in a slow clock period the timer value may not be cleared to zero yet if the timer is read immediately after the occurrence of the coincidence signal interrupt The count clock cannot be changed during timer operations 2 Compare registers 20 to ...

Page 165: ... the timer is cleared by the next clock tick If the division ratio is large and results in a slow clock period the timer value may not be cleared to zero yet if the timer is read immediately after the occurrence of the coincidence signal interrupt The count clock cannot be changed during timer operations 2 Capture compare register 3 CC3 CC3 is a 16 bit register connected to TM3 This register can b...

Page 166: ...0 1 the timer does not start 6 OST0 Overflow Stop Specifies the operation after overflow of timer 0 The timer continues counting after overflow has occurred 1 The timer retains 000000H and stops after overflow has occurred The timer resumes counting when the following operation is performed When ECLR0 0 writing 1 to CE0 bit When ECLR0 1 trigger inputting to timer clear pin TCLR0 3 to 0 PRM03 to Pr...

Page 167: ...pture compare register CC0n Set in combination with the IMS bit For the contents of the setting refer to the explanation of the IMS bit 3 to 0 IMS03 to Interrupt Mode Select IMS00 Selects the interrupt source Set in combination with the CMS bit CMS0n IMS0n CC0n Register Operation Mode Interrupt Source Selection 0 0 Operates as a capture register Interrupt is generated at capture timing 0 1 Setting...

Page 168: ...pt Source 0 0 Overflow interrupt is generated by TM0 0 1 Interrupt is generated by INTP04 1 0 Interrupt is generated by INTP05 1 1 Interrupt is generated by OR of INTP04 and INTP05 1 ECLR0 External Input Timer Clear Controls clear and start of TM0 by external clear input TCLR0 ECLR0 Clear and Start of TM0 0 TM0 is not cleared 1 TM0 is cleared and count up starts 0 CCLR0 Compare Input Timer Clear C...

Page 169: ...s counting when the following operation is performed Writing 1 to CE1 bit Writing 1 to CS1 bit 5 CS1 Clear Start Controls clear start of TM1 by software This bit is always 0 when writing 0 Continues counting 1 Clears TM1 and resumes counting 4 IMS1 Interrupt Mode Select Selects interrupt source 0 Interrupt occurs by overflow of TM1 1 Interrupt occurs by INTP14 signal 3 to 0 PRM13 to Prescaler Cloc...

Page 170: ... 0 Continues counting 1 Clears TM2n and resumes counting 3 to 0 PRM2n3 to Prescaler Clock Mode PRM2n0 Selects the count clock frequency PRM2n3 PRM2n2 PRM2n1 PRM2n0 Count Clock 0 0 0 1 φ 2 0 0 1 0 φ 4 0 0 1 1 φ 8 0 1 0 0 φ 16 0 1 0 1 φ 32 0 1 1 0 φ 64 0 1 1 1 φ 128 1 0 0 0 φ 256 1 1 1 1 TI2n input Others Setting prohibited Caution Do not change the count clock frequency while the timer operates Rem...

Page 171: ... This bit is always 0 when reading 0 Continues counting 1 Clears TM3 and resumes counting 4 CMS3 Capture Compare Mode Select Selects capture compare mode 0 Operates as a capture register 1 Operates as a compare register 3 to 0 PRM33 to Prescaler Clock Mode PRM30 Selects the count clock frequency PRM33 PRM32 PRM31 PRM30 Count Clock 0 0 0 1 φ 2 0 0 1 0 φ 4 0 0 1 1 φ 8 0 1 0 0 φ 16 0 1 0 1 φ 32 0 1 1...

Page 172: ...when coincidence signal is generated from corresponding compare register After the timer output has been enabled before the first coincidence signal is generated the anti phase levels of ALVn bit inactive levels are output 6 4 2 0 ALVn Active Level TO pin Specifies the active level of timer output 0 Active low 1 Active high Remarks 1 The flip flops of the TO00 and TO01 outputs is a reset priority ...

Page 173: ...ster is being read the overflow flag value will not be updated and this overflow condition will be reflected the next time the TOVS register is read Remark n 0 1 20 to 24 and 3 9 External interrupt mode registers 1 to 4 7 INTM1 to INTM4 INTM7 These registers set the following 3 types of valid edges Sets valid edge of external interrupt request signal INTP when using CP10 to CP13 timer 1 CC3 CP3 ti...

Page 174: ... is 1 timer 0 does not start counting until the TCLR0 signal is input Therefore it does not start counting by setting ECLR 0 after setting CE0 1 while ECLR0 1 Writing 1 to TM0 during counting operations CE0 1 does not clear the TM0 register and timer 0 continues counting 2 Stop counting Timer 0 stops counting by setting the CE0 bit to 0 If the OST bit of the TMC00 register is set to 1 timer 0 stop...

Page 175: ...M bit of the TMC00 register from φ 2 φ 4 φ 8 φ 16 φ 32 φ 64 φ 128 and φ 256 PRM03 PRM02 PRM01 PRM00 Internal Count Clock 0 0 0 1 φ 2 0 0 1 0 φ 4 0 0 1 1 φ 8 0 1 0 0 φ 16 0 1 0 1 φ 32 0 1 1 0 φ 64 0 1 1 1 φ 128 1 0 0 0 φ 256 2 External count clock The signal input to the TI0 pin is counted At this time timer 0 operates as an event counter To set an external count clock see the table as follows PRM0...

Page 176: ...s determined by the OST0 bit 1 Operation after occurrence of overflow when OST0 0 The TM0 register continues counting 2 Operation after occurrence of overflow when OST0 1 TM0 000000H is retained and the TM0 register stops counting At this time TM0 stops with CE0 1 Perform the following to resume counting When ECLR0 0 write 1 to CE0 bit When ECLR0 1 trigger input to timer clear pin TCLR0 The operat...

Page 177: ... set to 1 the count operation is started If the valid edge is input to TCLR0 during operation TM0 clears its value and then resume the count operation refer to Figure 7 3 When the valid edge is input to the TCLR0 signal after ECLR0 0 OST0 1 and the CE0 bit is set to 1 the count operation is started When TM0 overflows the count operation is stopped once and is not resumed until the valid edge is in...

Page 178: ...he CE0 bit is set to 1 the count operation is started If CC03 match is generated during operation TM0 clears its value and then resumes the count operation refer to Figure 7 5 If a value smaller than the current count value of TM0 is set to CC03 during count operation overflow of TM0 occurs refer to Figure 7 6 For the operation after occurrence of overflow refer to 7 4 3 Overflow Figure 7 5 Cleari...

Page 179: ...neously issued The value of the capture register is retained until the next capture trigger is generated When the capture timing to a capture register and write operation to a register by instruction are in contention the latter is given priority and the capture operation is ignored Table 7 2 Capture Trigger Signal to 24 Bit Capture Register Capture Trigger Signal Capture Register Interrupt Reques...

Page 180: ... even if the interrupt request INTP00 is input when CE0 is cleared to 0 Figure 7 8 Example of TM0 Capture Operation when both edges are specified Remark D0 to D2 count value of TM0 TM0 CE0 n 0 n Capture trigger CC00 INTP00 Capture trigger Capture trigger TM0 count value Interrupt request INTP00 Capture register CC00 CE0 1 Count starts OVF0 1 overflow D0 D1 D2 D1 D0 D2 FFFFFFH ...

Page 181: ...refer to Figure 7 9 The levels of the timer output pins TO can be changed by the coincidence signal and an interrupt request signal INTCC can be generated at the same time n 00 01 Table 7 3 Interrupt Request Signal from 24 Bit Compare Register Compare Register Interrupt Request Compare Match Trigger CC00 CC00L INTCC00 TO00 S CC01 CC01L INTCC01 TO00 R CC02 CC02L INTCC02 TO01 S CC03 CC03L INTCC03 TO...

Page 182: ...larly the count values of TM0 are compared with the values of CC00 When the two values coincide the output levels of the TO00 pin are set The count values of TM0 are also compared with the values of CC01 When the two values coincide the output levels of the TO00 pin are reset The output levels of the TOn pins can be specified by the TOC0 register n 00 01 Figure 7 10 Example of TM0 Compare Operatio...

Page 183: ...after occurrence of overflow However the value of the timer register can immediately be cleared by setting CE1 0 Figure 7 11 Basic Operation of Timer 1 7 5 2 Count clock selection An internal or external count clock frequency can be input to timer 1 Which count clock frequency is used is selected by the PRM10 to PRM13 bits of the TMC1 register Caution Do not change the count clock frequency while ...

Page 184: ...result of counting the TM1 register count clock frequency to FFFFFFH a flag is set to the OVF1 bits of the TOVS register and an overflow interrupt INTOV1 is generated The value of the OVF1 flag is retained until it is changed by user application The operation of the TM1 register after occurrence of overflow is determined by the OST1 bit 1 Operation after occurrence of overflow when OST1 0 The TM1 ...

Page 185: ...or the details of the operation refer to 7 5 3 Overflow 2 Clearing starting by software When the CS1 bit is set to 1 by software the TM1 register clears its value and starts counting from 0 However this setting of the bit is valid only when the value of the CE1 bit is 1 Figure 7 13 Clearing Starting Timer by Software when OST1 1 TM1 INTOV1 0 OST 1 CE1 1 CE1 1 Count starts Overflow FFFFFFH Overflow...

Page 186: ... register is retained until the next capture trigger is generated Table 7 4 Capture Trigger Signal to 24 Bit Capture Register Capture Trigger Signal Capture Register Interrupt Request INTP10 CP10 CP10L INTCP10 Divide of INTP11 CP11 CP11L INTCP11 Divide of INTP12 CP12 CP12L INTCP12 Divide of INTP12 INTP13 CP13 CP13L INTCP13 The valid edge of the INTP1n input is set by the external interrupt mode re...

Page 187: ...th CM10 is generated as a trigger of the real time output port An interrupt request signal INTCM can be generated at the same time Table 7 5 Interrupt Request Signal from 24 Bit Compare Register Compare Register Interrupt Request Compare Match Trigger CM10 CM10L INTCM10 Real time output port CM11 CM11L INTCM11 Figure 7 15 Example of Compare Operation Remark Note that the coincidence signal INTCM i...

Page 188: ...put in toggle Remark n 0 to 4 Figure 7 16 Basic Operation of Timer 2 7 6 2 Count clock selection An internal or external count clock frequency can be input to timer 2 Which count clock frequency is used is selected by the PRM2n0 to PRM2n3 bits of the TMC2n register n 0 to 4 Caution Do not change the count clock frequency while the timer operates 1 Internal count clock An internal count clock frequ...

Page 189: ...0 to 4 At the same time it generates an interrupt request signal INTCM20 to INTCM24 and a timer output trigger The interval time set to a compare register can be calculated by the following expression Set value 1 x Count cycle For the details refer to 7 6 5 Compare operation 2 Clearing starting by software When the value of the CS2n bit of the TMC2n register is set to 1 TM2n clears its value at th...

Page 190: ...FFH Remark Interval time N 1 count clock cycle N 1 to 65535 FFFFH Figure 7 18 When CM2n is Set to 0 Remark Interval time FFFFH 2 count clock cycle Count clock Count up TM2n clear TM2n CM2n Coincidence detected INTCM2n Overflow FFFFH 0 0 1 0 Clear Count clock Count up TM2n clear TM2n CM2n Coincidence detection INTCM2n Clear N 0 1 N ...

Page 191: ...are register CM20 to CM24 coincides with that of CM2n n 0 to 4 The relations between timers to be compared and compare register to timer outputs are shown below TM20 CM20 TO20 TM21 CM21 TO21 TM22 CM22 TO22 TM23 CM23 TO23 TM24 CM24 TO24 Figure 7 19 Example of Toggle Output Operation Remark n CM20 register value write by software TM20 count value 0H INTCM20 ALV20 ENTO20 TO20 output n n n n n CE20 1 ...

Page 192: ...erated Figure 7 20 Basic Operation of Timer 3 7 7 2 Count clock selection An internal count clock frequency is selected by the PRM30 to PRM33 bits of the TMC3 register from φ 2 φ 4 φ 8 φ 16 φ 32 φ 64 φ 128 and φ 256 Caution Do not change the count clock frequency while the timer operates PRM33 PRM32 PRM31 PRM30 Internal Count Clock Frequency 0 0 0 1 φ 2 0 0 1 0 φ 4 0 0 1 1 φ 8 0 1 0 0 φ 16 0 1 0 1...

Page 193: ...art counting from 0 However this setting of the bit is valid only when the value of the CE3 bit is 1 7 7 5 Capture operation When the TMC3 register is set as a capture register the capture compare register CC3 performs a capture operation that captures and holds the count value of TM3 and loads it to a capture register in synchronization with an external trigger and in asynchronization with the co...

Page 194: ...a compare register the capture compare register CC3 performs a comparison between the value in a compare register and the count value of TM3 When the count value of TM3 coincides with the value of the compare register programmed in advance clear and start of TM3 is performed and interrupt request signal INTCC3 is generated at the same time D0 D4 TM3 INTP30 CC3 trigger CP3 trigger CC3 CP3 INTCC3 0H...

Page 195: ...0 Figure 7 22 shows the timing Figure 7 23 illustrates the setting procedure Figure 7 22 Example of Timing of Interval Timer Operation timer 2 Remark n value of CM20 register t interval time n 1 x count clock cycle Figure 7 23 Setting Procedure of Interval Timer Operation timer 2 Interval timer initial setting Setting of TMC20 register Sets count value to CM20 register CM20 n Count starts TMC20 CE...

Page 196: ...ded as shown in Figure 7 24 To calculate the pulse width the difference between the count value of TM0 captured to the CC00 register on detection of the nth valid edge Dn and the count value on detection of the n 1 th valid edge Dn 1 is calculated This difference is multiplied by the count clock Figure 7 24 Pulse Width Measurement Timing timer 0 Remark D0 to D3 count value of TM0 FFFFFFH D0 D1 D3 ...

Page 197: ...egister Setting of INTM1 register INTM1 ES001 1 INTM1 ES000 1 Setting of TMC01 register TMC01 CMS00 0 TMC01 IMS00 0 Initialization of buffer memory for capture data storage X0 0 Count starts TMC00 CE0 1 Enables interrupt INTP00 interrupt Specifies count clock Specifies both edges as valid edge of INTP00 input signal Sets capture operation Sets CE0 bit to 1 Pulse width measurenent initial setting I...

Page 198: ...determined by the value set to capture compare register CC00 and the falling timing is determined by the value set to capture compare register CC01 The interval frequency of timer output can be changed freely by using compare coincidence of CC03 and by clearing and starting TM0 Figure 7 27 Example of PWM Output Timing Remark D00 to D02 D10 to D13 set value of compare register t1 1000000H D00 D01 x...

Page 199: ... TMC01 CMS00 1 TMC01 CMS01 1 Specifies P00 pin as timer output pin TO00 by PMC0 register PMC0 PMC00 1 Setting of TMC00 register Sets count value to CC00 register CC00 D00 Enables interrupt Count starts TMC00 CE0 1 Sets count value to CC01 register CC01 D10 Specifies active level high level Enables timer ouput Specifies operation of CC00 and CC01 registers specifies compare operation Sets CE0 bit t...

Page 200: ...xample of Interrupt Request Processing Routine Modifying Compare Value INTCC00 interrupt processing Sets time number of counts to reset TO00 output to 0 next to compare register CC01 RETI INTCC01 interrupt processing Sets time number of counts to set TO00 output to 1 next to compare register CC00 RETI ...

Page 201: ...dge To calculate the frequency the difference between the count value of TM0 captured to the CC00 register at the nth rising edge Dn and the count value captured at the n 1 th rising edge Dn 1 is calculated and the value multiplied by the count clock frequency The frequency measurement exceeding the maximum count value of TM0 is performed by counting the number of overflow with the INTOV0 overflow...

Page 202: ...ng of INTM1 register INTM1 ES01 0 INTM1 ES00 1 Initialization of buffer memory for capture data storage X0 0 Count starts TMC00 CE0 1 Enables interrupt INTP00 interrupt Specifies count clock of TM0 Specifies CC00 register as capture register Specifies rising edge as valid edge of INTP00 signal Sets CE0 bit to 1 Cycle measurement initial setting INTP00 interrupt processing Calculation of cycle Yn1 ...

Page 203: ... place in the following cases 1 When compare register is rewritten timer 0 to timer 3 2 When timer is cleared by external input timer 0 Count clock Value of timer Compare register value Coincidence detection n 1 n n 1 m Writing to register Coincidence does not occur Coincidence does not occur L n Value of timer External clear input Coincidence detection Count clock Compare register value n 1 n 0 0...

Page 204: ... timer 0 or timer 1 is operated as a free running timer the timer value is cleared to 0 when the timer overflows Notes 1 FFFFFEH for timer 0 2 FFFFFFH for timer 0 FFFEHNote 1 FFFFHNote 2 0 Coincidence does not occur Count clock Value of timer Internal coincidence clear 0 Coincidence detection Compare register value 0000H 1 Count clock Value of timer Overflow interrupt FFFEHNote 1 FFFFHNote 2 0 1 2...

Page 205: ... bus interface I2 C 1 channel µPD703008Y and 70F3008Y only The UART transmits receives 1 byte serial data following a start bit and can perform full duplex communication The CSI uses three signal lines to high speed synchronous data transfers data 3 wire serial I O serial clock SCKn serial input SIn and serial output SOn lines The I2 C uses two signal lines which are serial clock SCL and serial da...

Page 206: ...ull duplex communication internal receive buffer RXB Two pin configuration TXD transmit data output pin RXD receive data input pin Receive error detection function Parity error Framing error Overrun error Interrupt sources 3 Receive error interrupt INTSER Reception completion interrupt INTSR Transmission completion interrupt INTST Character length of transmit receive data is specified by ASIMn reg...

Page 207: ...ecked If an error is found the appropriate value is set to the ASIS registers 4 Receive shift register This shift register converts the serial data received on the RXD pin into parallel data When it receives 1 byte of data it transfers the receive data to the receive buffer This register cannot be directly operated 5 Receive buffers RXB RXBL RXB are 9 bit buffer registers that hold receive data If...

Page 208: ...onous Serial Interface Internal bus 16 8 8 Receive buffer Receive shift register Receive control parity check 1 16 1 16 1 2 INTST INTSR INTSER Transmission parity control Selector Selector φ Baud rate generator Internal system clock 8 8 16 8 ASIS RXD TXD PE FE OVE SOT RXE TXE PS1 PS0 CL SL SOLS EBS NOT ASIM0 ASIM1 RXB RXBL TXS TXSL Transmit shift register ...

Page 209: ... detect the start bit Data is not shifted into the receive shift register and neither is any transfer to the receive buffer performed Therefore the previous contents of the receive buffer are retained When reception is enabled the data is shifted into the receive shift register and transferred to the receive buffer when one complete frame has been received A reception completion interrupt INTSRn i...

Page 210: ...re 1 in receive data and parity bit are counted If it is odd parity error occurs Odd parity In contrast to even parity number of bits included in transmit data and parity bit that are 1 is controlled to become odd Since no parity bit check is performed during reception no parity error occurs 0 parity Parity bit is cleared to 0 during transmission regardless of transmit data Since no parity bit che...

Page 211: ...anteed if these registers are changed while UART is transmitting receiving data Remark φ Internal system clock Bit Position Bit Name Function 1 NOT Not Inverts the output level from TXD pin 0 Does not invert the output level 1 Inverts output level Use this function to connect an external circuit having inverted level to TXD pin 0 EBS Extended Bit Select Specifies extended bit operation of transmit...

Page 212: ...f the transmit shift register is ready to be written or not 2 PE Parity Error Status flag that indicates parity error Set 1 Transmit parity and receive parity do not match Clear 0 No error this flag is automatically cleared to 0 when the data is read from the receive buffer 1 FE Framing Error Status flag that indicates framing error Set 1 Stop bit is not detected Clear 0 No error this flag is auto...

Page 213: ...te where reception is disabled the data is not transfered into the reception buffer even when one complete frame of data has been shifted in and the data of the reception buffer is retained In addition the reception completion interrupt request is not generated RxB is only possible for reading in 16 bit units and RXBL in 8 1 bit units Bit Position Bit Name Function 8 RXEB Receive Extended Buffer E...

Page 214: ...o access the lower 8bits TXSL is specified TXS can only be written to TXS in 16 bit units and TXSL in 8 bit units Bit Position Bit Name Function 8 TXED Transmit Extended Data Extended bit on transmission of 9 bit character 7 to 0 TXS7 to Transmit Shifter TXS0 Writes transmit data Caution Since the UART does not have a transmit buffer an interrupt request due to the end of transmission is not gener...

Page 215: ...ve errors described in description of the ASIS registers when reception is enabled This interrupt does not occur when reception is disabled 2 Reception completion interrupt INTSR The reception completion interrupt occurs if data is received in the receive shift register and then transferred to the receive buffer when reception is enabled This interrupt also occurs when a receive error occurs but t...

Page 216: ...ansmission completion interrupt processing routine INTST a Transmission enabled status Set using the TXE bit of the ASIM0 register TXE 1 Transmission enabled status TXE 0 Transmission disabled status However to set the transmission enabled status set both the CTXE0 and CRXE0 bits of the clocked serial interface mode register CSIM0 to 0 Because the UART does not have a CTS transmission enabled sign...

Page 217: ...een completed Cautions 1 Generally the transmission completion interrupt INTST is generated when the transmit shift register TXS or TXSL is empty However by RESET input the transmission completion interrupt INTST is not generated when the transmit shift register TXS or TXSL is empty 2 During the transmit operation writing data into the TXS or TXSL register is ignored the data is discarded until IN...

Page 218: ...again eight clocks after the falling edge of the RXD pin has been detected If the RXD pin is low at this time it is recognized as the start bit and reception is started After that the RXD pin is sampled in 16 clock ticks If the RXD pin is high eight clocks after the falling edge of the RXD pin has been detected this falling edge is not recognized as the start bit The serial clock counter is reinit...

Page 219: ... interrupt INTSER can be identified The contents of the ASIS registers are reset to 0 when the receive buffer RXB or RXBL is read or the next data frame is received if the next data contains an error the corresponding error flag is set Receive Error Cause Parity error Parity specified during transmission does not coincide with parity of receive data Framing error Stop bit is not detected Overrun e...

Page 220: ...rs CSIM0 to CSIM3 CSIMn are 8 bit registers that specify the operation of CSIn 2 Serial I O shift registers SIO0 to SIO3 SIOn registers are 8 bit registers that convert serial data into parallel data and vice versa SIOn are used for both transmission and reception Data is shifted in received or shifted out transmitted from the MSB or LSB side The actual transmitting and receiving of data is actual...

Page 221: ...this pin connect it to VDD via a resistor Remark φ Internal system clock Internal bus CSIM0 CSI0 CTXE0 CRXE0 CSOT0 MOD0 CLS01 CLS00 SO latch D Q Serial I O shift register SIO0 SI0 SO0 SCK0 SI1 SO1Note CSI1 SCK1Note Serial clock control circuit Selector Selector 1 2 BRG0 2 φ φ Interrupt control circuit Serial clock counter INTCSI0 SI2 SO2 CSI2 SCK2 SI3 SO3 CSI3 SCK3 ...

Page 222: ...register If this bit is set to reception disabled status CRXEn 0 during receive operation the contents of the SIOn register become undefined 5 CSOTn CSI Status of Transmission Indicates that transfer operation is in progress Set 1 Transmission enable and start timing writing to SIO0 register Clear 0 Transmission cleared and end timing INTCSI occurs This bit is used to check whether writing to seri...

Page 223: ... is not guaranteed 2 Serial I O shift register 0 to 3 SIO0 to SIO3 These registers convert 8 bit serial data into parallel data and vice versa The actual transmitting and receiving of data is performed by writing data to and reading data from the SIOn registers A shift operation is performed when CTXE 1 or CRXE 1 These registers can be read written in 8 or 1 bit units Bit Position Bit Name Functio...

Page 224: ...SCKn SCKn stops when the serial clock counter overflows at the rising edge of the 8th count and SCKn remains high until the next data transmission or reception is started At the same time a transmission reception completion interrupt INTCSI is generated Caution If CTXE is changed from 0 to 1 after the transmit data is sent to the SIOn registers serial transfer will not begin Remark n 0 to 3 Remark...

Page 225: ...t is 0 When CRXEn bit 1 the serial input data is input to the shift register 3 To receive the transmit data and to check whether bus contention occurs set CTXEn bit and CRXEn bit to 1 b Starting transmission reception Transmission reception is started by reading writing the SIOn registers Transmission reception is controlled by setting the transmission enable bit CTXEn and reception enable bit CRX...

Page 226: ...ial clock is output from the SCKn pin and at the same time data is sequentially output to the SOn pin from SIOn in synchronization with the falling edge of the serial clock b When external clock is selected as serial clock When transmission is started the data is sequentially output from SIOn to the SOn pin in synchronization with the falling of the serial clock input to the SCKn pin immediately a...

Page 227: ...nputs are 0 2 Receiving data in synchronization with serial clock a When internal clock is selected as serial clock When reception is started the serial clock is output from the SCKn pin and at the same time data is sequentially loaded from the SIn pin to SIOn in synchronization with the rising edge of the serial clock b When external clock is selected as serial clock When reception is started the...

Page 228: ... Transmitting data in synchronization with serial clock a When internal clock is selected as serial clock When transmission reception is started the serial clock is output from the SCKn pin and at the same time data is sequentially set to the SOn pin from SIOn in synchronization with the falling edge of the serial clock Simultaneously the data of the SIn pin is sequentially loaded to SIOn in synch...

Page 229: ...l I O Mode transmission reception Remark n 0 to 3 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 1 2 3 4 5 6 7 8 SCKn SIn SOn INTCSIn Transfer starts in synchronization with falling edge of SCKn Execution of SIOn write instruction Serial transmission reception completion interrupt occurs ...

Page 230: ...peripheral I Os and display controllers that have a conventional clocked serial interface To connect two or more devices a handshake line is necessary Various devices can be connected because it can be specified whether the data is transmitted starting from the MSB or LSB Figure 8 10 Example of CSI System Configuration Remark n 0 to 3 3 wire serial l O 3 wire serial I O Master CPU SCKn SOn SIn Por...

Page 231: ... I2 C bus format Multi master serial bus Serial data automatic discrimination function Transfer speed standard mode 100 Kbps max high speed mode 400 Kbps max Chip select by address Wake up function Acknowledge signal ACK control function Wait signal WAIT control function Arbitration control function Conflict detection function ...

Page 232: ... clock SCL and the serial data bus SDA Conforming to I2 C bus format either start condition data or stop condition can be output onto serial data bus in transmission These data can be automatically detected by hardware in reception Because SCL and SDA are open drain outputs pull up resistors are required for the serial clock line and the serial data bus line Figure 8 11 Example of Serial Bus Confi...

Page 233: ... output N ch open drain output IICE LREL WREL SPIE WTIM ACKE STT SPT MSTS ALD EXC COI TRC ACKD STD SPD CLD DAD SMC DFC CL1 CL0 Slave address register SVA SO latch CL0 CL1 SET CLEAR Coincidence signal D Q Noise elimination circuit DFC Stop condition detection circuit Noise elimination circuit Serial clock counter Noise elimination circuit Prescaler IIC clock selection register IICL Internal system ...

Page 234: ... register that sets the local address with 8 bit memory manipulation instruction when used as a slave It becomes 00H by RESET input 3 SO latch Retains SDA pin output level 4 Wake up control circuit Generates interrupt requests when the address value set in the slave address register SVA and the reception address coincide or when an extension code is received 5 Clock selector Selects the sampling c...

Page 235: ...lock in the master mode 9 Serial clock wait control circuit Controls wait timings 10 Acknowledgeoutputcircuit stopconditiondetectioncircuit startconditiondetectioncircuit acknowledge detection circuit Performs output and detection of various control signals 11 Data retention time correction circuit Generates data retention time for the fall of the serial clock ...

Page 236: ... 8 4 4 Serial interface control register I2 C bus is controlled by the following three registers IIC control register IICC IIC status register IICS IIC clock selection register IICCL The following registers are also used IIC shift register IIC Slave address register SVA ...

Page 237: ...its from communication and enters wait status This bit is used when an extension code not related to the local register is received SCL and SDA lines go into high impedance status The following flags are cleared EXC ACKD COI MSTS TRC STD Set condition Instruction Clear condition Reset input or automatically cleared after execution 5 WREL Wait Release Selects whether releasing wait or not 0 Does no...

Page 238: ... and valid when EXC 1 Set condition Instruction Clear condition Instruction reset input 1 STT Start Condition Trigger Selects whether generating start condition or not 0 Does not generate start condition 1 Generates start condition When bus is released stop status generates start condition by changing SDA line from high level to low level starts up as master And then secures specification time and...

Page 239: ...on Arbitration defeat Clear condition IICE 0 reset input or after IICS read A bit manipulation instruction is executed to another bit of the IICS register 5 EXC Extension Code Indicates reception of extension code 0 Extension code is not received 1 Extension code is received Set condition The higher 4 bits of the received address are 0000 or 1111 set at the rise of the eighth clock Clear condition...

Page 240: ...ndicates detection of acknowledge signal 0 Not detected 1 Detected Set condition SDA line becomes low level at the rise of the ninth clock of SCL Clear condition LREL 1 the rise of the first clock of the next byte stop condition detection IICE 0 or reset input 1 STD Start Condition Detected Indicates detection of start condition 0 Start condition not detected 1 Start condition detected Indicates a...

Page 241: ...eration 0 OFF 1 ON Digital filter can be used in high speed mode The response becomes slow when digital filter is used 1 0 CL1 CL0 Clock Selects internal clock according to the system clock CL1 CL0 Standard Mode High speed Mode Transfer clock Transfer clock DFC 0 DFC 1 DFC 0 DFC 1 0 0 φ 4 0 to 8 0 MHz φ 88 φ 92 φ 8 0 to 16 0 MHz φ 48 φ 48 0 1 φ 10 0 to 16 0 MHz φ 172 φ 176 φ 8 0 to 16 0 MHz φ 48 φ...

Page 242: ...follows a SCL Pin to input output serial clock Output is N ch open drain both for master and slave Input is Schmitt input b SDA I O multiplexed pin for serial data Output is N ch open drain both for master and slave Input is Schmitt input Because the outputs of serial clock line and the serial data bus line are N ch open drain external pull up resistors are required Figure 8 13 Pin Configuration C...

Page 243: ... is kept being output from the master However the slave can extend the low level period of SCL and insert wait 1 Start condition The start condition is generated when the SDA pin changes from high level to low level while the SCL pin is high level The start condition of the SCL pin and the SDA pin is a signal which is the master outputs to the slave when a serial transfer starts The slave is provi...

Page 244: ...ter SVA When the 7 bit data and the value of SVA coincide a slave is selected and the slave performs communication with the master until the master transmits a start or stop condition Figure 8 16 Address Note INTIIC is not generated if address other than the local address or extension code is received while the slave operates The address is output when the 8 bit address consisting of the slave add...

Page 245: ... direction specification bit is 0 the master transmits data to the slave When the transmit direction specification bit is 1 the master receives data from the slave Figure 8 17 Transfer Direction Specification Note INTIIC is not generated if address other than the local address or extension code is received while the slave operates A6 A5 A4 A3 Transfer direction specification A2 A1 A0 R W Note 1 2 ...

Page 246: ... the acknowledge signal automatic generation enable status is set The TRC bit of the IICS register is set according to the data of the eighth bit following the 7 bit address information However when the value of the TRC bit is 0 set ACKE 1 because it is receive status In the slave receive operation TRC 0 if the slave side has received two or more bytes and needs the next data set ACKE 0 so that th...

Page 247: ...n is a signal which the master outputs to the slave when a serial transfer has ended The slave is provided with the hardware to detect the stop condition Figure 8 19 Stop Condition The stop condition is generated by setting to 1 bit 0 SPT of the IICC control register IICC When the stop condition is detected bit 0 SPD of the IICC status register IICS is set 1 When bit 4 SPIE of IICC is set 1 INTIIC...

Page 248: ... SCL pin Both the master and slave can start the next transfer when the wait status is released Figure 8 20 Wait Signal 1 2 1 When the master is 9 clock wait and the slave is 8 clock wait master transmission slave reception ACKE 1 6 7 8 1 2 3 9 SCL 6 7 8 1 2 3 9 D2 D1 D0 D7 D6 D5 ACK SCL SDA IIC Master Slave Transfer line Slave is waiting low level while master returns to Hi Z Waits after outputti...

Page 249: ... the receive side releases wait when WREL 1 or when FFH is written to IIC and the transmit side releases wait when data is written to IIC For the master wait can be released also with the following method STT 1 SPT 1 6 7 8 1 2 3 9 SCL 6 7 8 1 2 3 9 D2 D1 D0 D7 D6 D5 ACK SCL SDA IIC Master Slave Transfer line Both master and slave wait after outputting the ninth clock IIC data wait released SCL ACK...

Page 250: ... Stop normal transmission reception 1 When WTIM 0 1 IICS 10 x x x 11 0 B 2 IICS 10 x x x 00 0 B 3 IICS 10 x x x 00 0 B 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 1 IICS 10 x x x 11 0 B 2 IICS 10 x x x 10 0 B 3 IICS 10 x x x x 0 0 B 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 AK AK SP AD6 to AD...

Page 251: ... 5 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 1 IICS 10 x x x 11 0 B 2 IICS 10 x x x x 0 0 B 3 IICS 10 x x x 11 0 B 4 IICS 10 x x x x 0 0 B 5 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 RW AK AD6 to AD0 AD6 to AD0 AK ST D7 to D0 AK SP D7 to D0 2 3 4 5 ST RW AK 1 RW AK AD6 to AD0 AD6 to AD0 AK ST D...

Page 252: ... 0 B 3 IICS 1010 x 00 0 B 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 1 IICS 1010 x 11 0 B 2 IICS 1010 x 10 0 B 3 IICS 1010 x x 0 0 B 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 AK AK SP AD6 to AD0 D7 to D0 D7 to D0 2 3 4 ST RW AK 1 AK AK SP AD6 to AD0 D7 to D0 D7 to D0 2 3 4 ...

Page 253: ... B 2 IICS 0001 x 00 0 B 3 IICS 0001 x 00 0 B 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 1 IICS 0001 x 11 0 B 2 IICS 0001 x 10 0 B 3 IICS 0001 x x 0 0 B 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 AK AK SP AD6 to AD0 D7 to D0 D7 to D0 2 3 4 ST RW AK 1 AK AK SP AD6 to AD0 D7 to D0 D7 to D0 2 3 4...

Page 254: ...ICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 SVA coincides after restart 1 IICS 0001 x 11 0 B 2 IICS 0001 x x 0 0 B 3 IICS 0001 x 11 0 B 4 IICS 0001 x x 0 0 B 5 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 RW AK AD6 to AD0 AD6 to AD0 AK ST D7 to D0 AK SP D7 to D0 2 3 4 5 ST RW AK 1 RW AK AD6 to AD0 AD...

Page 255: ... 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 receives extension code after restart 1 IICS 0001 x 11 0 B 2 IICS 0001 x x 0 0 B 3 IICS 0010 x 01 0 B 4 IICS 0010 x 11 0 B 5 IICS 0010 x x 0 0 B 6 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 RW AK AD6 to AD0 AD6 to AD0 AK ST D7 to D0 AK SP D7 to D0 2 3 4 5 ST RW AK 1 ...

Page 256: ...4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 address does not coincide after restart except extension code 1 IICS 0001 x 11 0 B 2 IICS 0001 x x 0 0 B 3 IICS 0000 x x 1 0 B 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 RW AK AD6 to AD0 AD6 to AD0 AK ST D7 to D0 AK SP D7 to D0 2 3 4 ST RW AK 1 RW AK...

Page 257: ...B 3 IICS 0010 x 00 0 B 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 1 IICS 0010 x 01 0 B 2 IICS 0010 x 11 0 B 3 IICS 0010 x x 0 0 B 4 IICS 0010 x x 0 0 B 5 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 AK AK SP AD6 to AD0 D7 to D0 D7 to D0 2 3 4 ST RW AK 1 AK AK SP AD6 to AD0 D7 to D0 D7 to D0 3 2 4...

Page 258: ...1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 SVA coincides after restart 1 IICS 0010 x 01 0 B 2 IICS 0010 x 11 0 B 3 IICS 0010 x x 0 0 B 4 IICS 0001 x 11 0 B 5 IICS 0001 x x 0 0 B 6 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 RW AK AD6 to AD0 AD6 to AD0 AK ST D7 to D0 AK SP D7 to D0 2 3 4 5 ST RW AK 1 RW AK AD6 t...

Page 259: ...lways generates generates only when SPIE 1 x don t care 2 When WTIM 1 receives extension code after restart 1 IICS 0010 x 01 0 B 2 IICS 0010 x 11 0 B 3 IICS 0010 x x 0 0 B 4 IICS 0010 x 01 0 B 5 IICS 0010 x 11 0 B 6 IICS 0010 x x 0 0 B 7 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 RW AK AD6 to AD0 AD6 to AD0 AK ST D7 to D0 AK SP D7 to D0 2 3 4 5 ST ...

Page 260: ...00 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 address does not coincides after restart except extension code 1 IICS 0010 x 01 0 B 2 IICS 0010 x 11 0 B 3 IICS 0010 x x 0 0 B 4 IICS 0000 0 x 1 0 B 5 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 RW AK AD6 to AD0 AD6 to AD0 AK ST D7 to D0 AK SP D7 to D0 2 3 4 ST RW A...

Page 261: ...t operates as a slave after arbitration defeat i When defeated in arbitration during slave address data transmission 1 When WTIM 0 1 IICS 0101 x 11 0 B example reads ALD during interrupt processing 2 IICS 0001 x 00 0 B 3 IICS 0001 x 00 0 B 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 AK AK SP AD6 to AD0 D7 to D0 D7 to D0 2 3 4 ST RW AK AK AK SP AD6...

Page 262: ...nerates generates only when SPIE 1 x don t care ii When defeated in arbitration during transmitting extension code 1 When WTIM 0 1 IICS 0110 x 01 0 B example reads ALD during interrupt processing 2 IICS 0010 x 00 0 B 3 IICS 0010 x 00 0 B 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 AK AK SP AD6 to AD0 D7 to D0 D7 to D0 2 3 4 ST RW AK 1 AK AK SP AD6...

Page 263: ...always generates generates only when SPIE 1 x don t care f Operation of arbitration defeat does not join after arbitration defeat i When defeated in arbitration during transmitting slave address data 1 IICS 0100 011 0 B example reads ALD during interrupt processing 2 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 ST RW AK 1 AK AK SP AD6 to AD0 D7 to D0 D7 to D0 3 2 4 5 ST RW ...

Page 264: ...joining communication 2 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care iii When defeated in arbitration during transferring data 1 When WTIM 0 1 IICS 1000 111 0 B 2 IICS 0100 000 0 B example reads ALD during interrupt processing 3 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 ST RW AK AK AK SP AD6 to AD0 D7 to D0 D7 to D0 1 2 ST RW AK AK AK...

Page 265: ...when SPIE 1 iv When defeated in restart condition during transferring data 1 Except extension code example SVA does not coincide 1 IICS 1000 x 11 0 B 2 IICS 0100 011 0 B example reads ALD during interrupt processing 3 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care n 0 to 6 ST RW AK AK AK SP AD6 to AD0 D7 to D0 D7 to D0 1 2 3 ST RW AK 1 RW AK AD6 to AD0 AD6 to AD0...

Page 266: ... when not joining communication 3 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care n 0 to 6 v When defeated in stop condition during transferring data 1 IICS 1000 x 11 0 B 2 IICS 0100 000 1 B Remark always generates generates only when SPIE 1 x don t care n 0 to 6 ST RW AK 1 RW AK AD6 to AD0 AD6 to AD0 ST D7 to Dn AK SP D7 to D0 2 3 ST RW AK 1 AD6 to AD0 D7 to Dn S...

Page 267: ...ALD during interrupt processing 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 1 IICS 1000 x 11 0 B 2 IICS 1000 x x 0 0 B 3 IICS 0100 010 0 B example reads ALD during interrupt processing 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 AK AD6 to AD0 D7 to D0 AK STT 1 D7 to D0 AK SP D7 to D0 2 3 4 ST R...

Page 268: ...s low level 1 When WTIM 0 1 IICS 1000 x 11 0 B 2 IICS 1000 x 00 0 B 3 IICS 0100 000 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 1 IICS 1000 x 11 0 B 2 IICS 1000 x x 0 0 B 3 IICS 0100 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 AD6 to AD0 AK STT 1 D7 to D0 SP 2 3 ST RW AK 1 AD6 to AD0 AK STT 1 D7 to D0 SP 2 3 ...

Page 269: ...ALD during interrupt processing 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care 2 When WTIM 1 1 IICS 1000 x 11 0 B 2 IICS 1000 x x 0 0 B 3 IICS 0100 000 0 B example reads ALD during interrupt processing 4 IICS 0000 000 1 B Remark always generates generates only when SPIE 1 x don t care ST RW AK 1 AK AD6 to AD0 D7 to D0 AK SPT 1 D7 to D0 AK SP D7 to D0 2 3 4 ST R...

Page 270: ... and the received address do not coincide Remark The numbers in the table represent the number of the clocks of the serial clock Both the interrupt request and the wait control synchronize with the fall of the serial clock a When transmitting receiving address In slave operation The interrupt and the wait timings are determined regardless of the WTIM bit In master operation The interrupt and the w...

Page 271: ... bit address transfer and 111110xx0 is transferred from the master However interrupt request INTIIC generates at the fall of the eighth clock Coincidence of the higher 4 bit data EXC 1 Coincidence of the 7 bit data COI 1 c The processing after interrupt request is issued differs depending on the data following the extension code Therefore it is performed by software For example LREL is set to 1 an...

Page 272: ...ote 2 Attempted to output restart condition but data is low level Fall of the eighth or ninth clock after byte transferNote 1 Attempted to output restart condition but stop condition is detected Stop condition output SPIE 1 Note 2 Attempted to output stop condition but data is low level Fall of the eighth or ninth clock after byte transfer Attempted to restart condition but SCL is low level Notes ...

Page 273: ...lave receiving an extension code when not sending back ACK and releasing bus with LREL of IICC 1 When the STT bit of the IICC is set in the status not joining the bus a start condition is automatically generated and wait status is entered after the bus is released stop condition detection When the bus release is detected stop condition detection address transfer as a master is started by IIC write...

Page 274: ...lowing timings The communication reservation is made by setting the STT of IICC 1 before stop condition detection after STD of IICS 1 is set Wait status SPD STD SDA SCL 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 Output by the master which has occupied the bus Program processing Hardware processing Setting SPD and INTIIC Setting STD Commu nication reserva tion IIC write SCL SDA STT 1 ...

Page 275: ...release bus before starting master communication In multi master master communication cannot be performed in the status in which bus is not released stop condition is not detected Generate stop condition with the following procedure 1 Setting IICCL 2 IICE of IICC 1 3 SPT of IICC 1 DI STT 1 Definition of communication reservation Wait Cancellation of communication reservation IIC xxH EI STT 1 Sets ...

Page 276: ...aster communication state confirm that the TRC bit is 1 transmission operation At this time if the TRC bit is 0 set LREL to withdraw from communication and carry out communication reservation STT 1 again after the stop condition is detected d STT setting timing when a multi master is used Arrange the program as shown in Figure 8 24 Figure 8 24 STT Setting Timing Procedure Caution The period of tim...

Page 277: ...r clock IICC xxH IICE SPIE WTIM 1 STT 1 Generates stop condition absence of slave of the address coincidence IIC write Transfer starts WTIM 0 ACKE 1 INTIIC 1 Detects stop condition Address transfer ends Yes Transmission Yes Yes Yes INTIIC 1 ACKD 1 TRC 1 INTIIC 1 ACKD 1 Data processing ACKE 0 WREL 1 Reception starts INTIIC 1 Transfer ends No Reception No Yes No Yes No Yes No No Yes No No IIC write ...

Page 278: ...ve Operation Procedure START Data processing IICC xxH IICE 1 WTIM 0 ACKE 1 INTIIC 1 Yes Yes No Yes EXC 1 COI 1 TRC 1 INTIIC 1 ACKD 1 Data processing LREL 1 ACKE 0 WREL 1 Reception starts INTIIC 1 Transfer ends No No Yes Joining communication No Yes No Yes No Yes No No Yes Yes No WTIM 1 IIC write Transfer starts Generates restart condition or stop condition ...

Page 279: ...t indicates the transfer direction of data following the slave address and starts serial communication with the slave Figures 8 27 and 8 28 show the timing charts of data communication The shift operation of the shift register IIC is performed in synchronization with the fall of the serial clock SCK the transmitted data is transferred to the SO latch and output from the SDA pin with the MSB first ...

Page 280: ...rm wait release of a slave with either IIC FFH or WREL 1 IIC Processing of master device IIC Address IIC Data ACKD STD SPD WTIM ACKE STT SPT WREL INTIIC MSTS TRC SCL SDA A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 1 2 3 4 1 2 3 4 5 6 7 8 9 W ACK Start condition H IIC ACKD STD SPD WTIM ACKE H H H H L Reception Note When EXC 1 L STT SPT WREL INTIIC MSTS TRC IIC FFHNote Transmission Processing of slave device T...

Page 281: ...wait release of a slave with either IIC FFH or WREL 1 IIC Processing of master device IIC Data IIC Data ACKD STD SPD WTIM ACKE STT SPT WREL INTIIC MSTS TRC SCL SDA D7 D0 D6 D5 D4 D3 D2 D1 D7 D6 D5 1 2 3 1 2 8 9 3 4 5 6 7 8 9 D0 H H H H H H IIC ACKD STD SPD WTIM ACKE L Reception Note Note L STT SPT WREL INTIIC MSTS TRC IIC FFHNote IIC FFHNote Transmission Processing of slave device Transfer line ...

Page 282: ...lave with either IIC FFH or WREL 1 IIC Processing of master device IIC Data IIC Address ACKD STD SPD WTIM ACKE STT SPT WREL INTIIC MSTS TRC SCL SDA D7 D6 D5 D4 D3 D2 D1 A6 A5 1 2 1 2 3 4 5 6 7 8 9 D0 ACK H H H H H IIC ACKD STD SPD WTIM ACKE L Reception Note Note When SPIE 1 When SPIE 1 L STT SPT WREL INTIIC MSTS TRC IIC FFHNote IIC FFHNote Transmission Processing of slave device Transfer line Star...

Page 283: ...dress Note Perform wait release of a slave with either IIC FFH or WREL 1 IIC Processing of master device IIC Address IIC FFHNote ACKD STD SPD WTIM ACKE H H STT SPT WREL Note INTIIC MSTS TRC SCL SDA A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 R Start condition IIC ACKD STD SPD WTIM ACKE H H L STT SPT WREL INTIIC MSTS TRC IIC Data Processing of slave device Transfer line ...

Page 284: ... release of a slave with either IIC FFH or WREL 1 IIC Processing of master device IIC FFHNote IIC FFHNote ACKD STD SPD WTIM ACKE STT SPT WREL INTIIC MSTS TRC SCL SDA D7 ACK D0 D6 D5 D4 D3 D2 D1 D7 D6 D5 1 2 3 1 2 8 9 3 4 5 6 7 8 9 D0 L H H H H H IIC ACKD STD SPD WTIM ACKE L Transmission Note Note H STT SPT WREL INTIIC MSTS TRC IIC Data IIC Data Reception Processing of slave device Transfer line AC...

Page 285: ...m wait release of a slave with either IIC FFH or WREL 1 IIC Processing of master device IIC FFHNote IIC Address ACKD STD SPD WTIM ACKE STT SPT WREL INTIIC MSTS TRC SCL SDA D7 D6 D5 D4 D3 D2 D1 A6 A5 1 2 1 2 3 4 5 6 7 8 9 D0 N ACK H H H H IIC ACKD STD SPD WTIM ACKE L Note When SPIE 1 When SPIE 1 STT SPT WREL INTIIC MSTS TRC IIC Data Processing of slave device Transfer line Start condition Stop cond...

Page 286: ...h can be set independently For UART CSI0 BRG0 For I2 C CSI1 BRG1 For CSI2 BRG2 For CSI3 BRG3 The serial clock source for the UART is specified by the SCLS bits of the ASIMn registers The serial clock source for the CSI is specified by the CLS bits of the CSIMn registers When the output of the baud rate generator is specified the baud rate generator will be used as the clock source Because the seri...

Page 287: ...M00 287 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8 29 Block Diagram of Baud Rate Generator Internal bus BRGC0 BRG0 BPRM0 BRCE0 BPR02 BPR01 BPR00 Coincidence Clear TMBRG0 BRG1 Prescaler UART CSI0 φ CSI1 I2 C BRG2 CSI2 BRG3 CSI3 ...

Page 288: ... expression because a sample rate of x16 is used Baud rate bps where φ Internal system clock frequency Hz m BRGC0 set up value 1 m 256Note k BPR00 to BPR02 prescaler set up value Note 256 is set by writing 0 to the BRGC0 register ii CSI0 to CSI3 If the dedicated baud rate generator is specified for CSIn the actual baud rate can be calculated by the following expression n 0 to 3 Baud rate bps where...

Page 289: ... 20 1 73 0 13 0 16 0 10 1 73 76800 0 13 3 29 0 10 1 73 0 6 6 99 Note 0 5 1 73 153600 0 7 1 30 0 5 1 73 0 3 8 51 Note Baud Rate bps φ 19 660 MHz φ 14 746 MHz φ 12 288 MHz φ 9 830 MHz BPR BRGC Error BPR BRGC Error BPR BRGC Error BPR BRGC Error 110 5 176 0 83 5 131 0 07 4 218 0 08 4 176 0 02 150 5 128 0 00 4 192 0 00 4 160 0 00 4 128 0 00 300 4 128 0 00 3 192 0 00 3 160 0 00 3 128 0 00 600 3 128 0 00...

Page 290: ... 73 614400 1 13 3 29 1 10 1 73 1 7 6 99 Note 1 5 1 73 1228800 1 7 4 09 1 5 1 73 1 3 15 2 Note 2457600 1 3 11 30 Note 1 2 27 2 Note Baud Rate bps φ 20 MHz φ 14 746 MHz φ 12 288 MHz φ 9 830 MHz BPR BRGC Error BPR BRGC Error BPR BRGC Error BPR BRGC Error 1760 5 178 0 25 5 131 0 07 4 218 0 08 4 176 0 26 2400 5 130 0 16 4 192 0 00 4 160 0 00 4 128 0 00 4800 4 130 0 16 3 192 0 00 3 160 0 00 3 128 0 00 9...

Page 291: ... an error 8 5 2 Baud rate generator compare registers 0 to 3 BRGC0 to BRGC3 These are 8 bit compare registers that set a timer count value for the dedicated baud rate generator These registers can be read written in 8 or 1 bit units Caution The internal timer TMBRGn is cleared by writing the BRGC registers Therefore do not rewrite or program the BRGCn registers during transmission reception operat...

Page 292: ...n0 Baud Rate Generator Prescaler Specifies count clock input to internal timer TMBRGn BPRn2 BPRn1 BPRn0 Count Clock 0 0 0 φ k 0 CSI use disabled 0 0 1 φ 2 k 1 0 1 0 φ 4 k 2 0 1 1 φ 8 k 3 1 0 0 φ 16 k 4 1 0 1 φ 32 k 5 Others Setting prohibited k Set value of prescaler φ Internal system clock Caution Do not change the count clock during transmission reception operation Remark n 0 to 3 Address FFFFF0...

Page 293: ...by the ASIM0 register and the CSIM0 register ASIM0 Register CSIM0 Register Selection of Operational Peripheral I O TXE RXE CTXE0 CRXE0 0 0 0 0 Operation stops 0 1 0 0 Selects UART 1 0 0 0 1 1 0 0 0 0 0 1 Selects CSI 0 0 1 0 0 0 1 1 Others Setting prohibited 2 Selecting CSI1 or I2 C The setting is made by the IICC register and the CSIM1 register IICC Register CSIM1 Register Selection of Operational...

Page 294: ...294 User s Manual U11969EJ3V0UM00 MEMO ...

Page 295: ...arator Compares the voltage difference between the input analog input and voltage tap of the serial resistor string output 4 Serial resistor string Generates voltage to coincide with analog input The serial resistor string is connected between the reference voltage pin for A D converter AVREF and GND pin for A D converter AVSS The serial resistor consists of 255 equivalent resistors and two resist...

Page 296: ...pecially if the voltage exceeding VDD or less than VSS even if it is within the range of the absolute maximum rating is input the conversion value of the channel may become undefined or the conversion value of other channels may be affected 9 AVREF pin Pin for inputting the reference voltage of the A D converter Converts signals input to the ANI0 to ANI5 pins to digital signals based on the voltag...

Page 297: ... is executed from the beginning Bit 6 cannot be written in and writing executed is ignored Bit Position Bit Name Function 7 CE Convert Enable Enables or disables A D conversion operation 0 Disabled 1 Enabled 6 CS Converter Status Indicates the status of A D converter This bit is read only 0 Stops 1 Operates 5 BS Buffer Select Specifies buffer mode in the select mode 0 1 buffer mode 1 4 buffer mode...

Page 298: ... to ANI4 ANI8 to ANI12 1 0 1 ANI5 ANI13 ANI0 to ANI5 ANI8 to ANI13 1 1 0 ANI6 ANI14 ANI0 to ANI6 ANI8 to ANI14 1 1 1 ANI7 ANI15 ANI0 to ANI7 ANI8 to ANI15 Caution When the CE bit is 1 in the timer trigger mode and external trigger mode the trigger signal standby state is set To clear the CE bit write 0 or reset In the A D trigger mode the conversion trigger is set by writing 1 to the CE bit After ...

Page 299: ...0 External trigger mode 1 1 Setting prohibited 2 to 0 FR2 to FR0 Frequency Specifies conversion operation time FR2 FR1 FR0 Number of Conversion Operation Time µs Conversion Clock φ 33 MHz φ 25 MHz φ 16 MHz 0 0 0 50 3 1 0 0 1 60 3 8 0 1 0 80 3 2 5 0 0 1 1 100 3 0 4 0 6 3 1 0 0 120 3 6 4 8 7 5 1 0 1 140 4 2 5 6 8 8 1 1 0 180 5 4 7 2 11 3 1 1 1 200 6 0 8 0 12 5 3 A D conversion result register ADCR0 ...

Page 300: ...1 ANI9 ADCR1 ANI2 ANI10 ADCR2 ANI3 ANI11 ADCR3 ANI4 ANI12 ADCR4 ANI5 ANI13 ADCR5 ANI6 ANI14 ADCR6 ANI7 ANI15 ADCR7 Figure 9 2 shows the relation between the analog input voltage and the A D conversion result Figure 9 2 Relation between Analog Input Voltage and A D Conversion Result 0 1 512 1 2 3 A D conversion result ADCRn 253 254 255 1 256 3 512 2 256 5 512 3 256 Input voltage AVREF 507 512 254 2...

Page 301: ...on the A D conversion operation started before the change is stopped and the conversion results are not stored in the ADCRn register n 0 to 7 2 During the timer trigger mode and external trigger mode if the CE bit of the ADM0 register is set to 1 the mode changes to the trigger standby state The A D conversion operation is started by the trigger signal and the trigger standby state is returned whe...

Page 302: ...nversion timing of the analog input set for the ANI0 to ANI15 pins using the values set to the RPU compare register This register creates the analog input conversion timing by generating the coincidence interrupts of the capture compare registers CC03 connected to the 24 bit TM10 c External trigger mode Mode which specifies the conversion timing of the analog input to the ANI0 to ANI15 pins using ...

Page 303: ...r mode A D converts one analog input specified by the ADM0 register The conversion results are stored in the ADCRn register corresponding to the analog input The analog input and ADCRn register correspond one to one and an A D conversion end interrupt INTAD is generated each time one A D conversion ends Figure 9 3 Operation Timing Example of Select Mode 1 Buffer Mode ANI1 ANI0 ANI1 ANI2 ANI3 ANI4 ...

Page 304: ... generated when the four A D conversions end Figure 9 4 Operation Timing Example of Select Mode 4 Buffer Mode ANI6 1 2 ANI6 A D conversion Data 1 ANI6 Data 2 ANI6 Data 3 ANI6 Data 4 ANI6 Data 5 ANI6 Data 4 Data 5 Data 6 ANI6 Data 7 ANI6 Data 1 ANI6 ADCR4 Data 2 ANI6 ADCR5 Data 3 ANI6 ADCR6 Data 4 ANI6 ADCR7 Data 6 ANI6 ADCR4 Data 1 Data 2 Data 3 Data 6 Data 7 ADCR INTAD Conversion starts ADM0 sett...

Page 305: ...0 305 Figure 9 4 Operation Timing Example of Select Mode 4 Buffer Mode ANI6 2 2 ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 A D converter ADCR register Analog input ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 ...

Page 306: ...version of the specified analog input ends the INTAD interrupt is generated n 0 to 7 Figure 9 5 Operation Timing Example of Scan Mode 4 Channel Scan ANI0 to ANI3 1 2 ANI3 ANI0 ANI1 ANI2 A D conversion Data 1 ANI0 Data 2 ANI1 Data 3 ANI2 Data 4 ANI3 Data 5 ANI0 Data 4 Data 5 Data 6 ANI0 Data 7 ANI1 Data 1 ANI0 ADCR0 Data 2 ANI1 ADCR1 Data 3 ANI2 ADCR2 Data 4 ANI3 ADCR3 Data 6 ANI0 ADCR0 Data 1 Data...

Page 307: ...7 Figure 9 5 Operation Timing Example of Scan Mode 4 Channel Scan ANI0 to ANI3 2 2 ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 A D converter ADCR register Analog input ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 ...

Page 308: ...alog input and ADCRn register correspond one to one Refer to Table 9 1 Figure 9 6 Each time an A D conversion is executed an INTAD interrupt is generated and the AD conversion terminates When 1 is written to the CE bit of the ADM0 register A D conversion can be restarted This mode is suitable for applications which read out the result in each A D conversion Table 9 1 Correspondence between Analog ...

Page 309: ...ations which calculate the average of the A D conversion result Table 9 2 Correspondence between Analog Input Pin and ADCRn Register 4 buffer mode A D trigger select 4 buffer Analog Input A D Conversion Results Register ANI0 to ANI3 ANI8 to ANI11 ADCR0 First time ADCR1 Second time ADCR2 Third time ADCR3 Fourth time ANI4 to ANI17 ANI12 to ANI15 ADCR4 First time ADCR5 Second time ADCR6 Third time AD...

Page 310: ...nded When 1 is written to the CE bit of the ADM0 register A D conversion can be restarted This mode is suitable for applications which always monitor two or more analog inputs Table 9 3 Correspondence between Analog Input Pin and ADCRn Register scan mode A D trigger scan Analog Input A D Conversion Results Register ANI0 ANI8 ADCR0 ANI1 ANI9 ADCR1 ANI2 ANI10 ADCR2 ANI3 ANI11 ADCR3 ANI4 ANI12 ADCR4 ...

Page 311: ...ence interrupt signal INTCC03 A D conversion trigger of the compare register is repeatedly output and A D conversion is also repeated Coincidence of the compare register can also clear TM0 and restart it 9 6 1 Select mode operation The A D converter converts an analog input ANI0 to ANI15 specified by the ADM0 register The conversion results are stored in the ADCRn register corresponding to the ana...

Page 312: ...interrupt ANI1 ANI9 ADCR1 INTCC03 interrupt ANI2 ANI10 ADCR2 INTCC03 interrupt ANI3 ANI11 ADCR3 INTCC03 interrupt ANI4 ANI12 ADCR4 INTCC03 interrupt ANI5 ANI13 ADCR5 INTCC03 interrupt ANI6 ANI14 ADCR6 INTCC03 interrupt ANI7 ANI15 ADCR7 Figure 9 9 Example of 1 Buffer Mode timer trigger select 1 buffer Operation ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 IN...

Page 313: ... the CE bit is set to 1 the INTAD interrupt is not generated and the standby state is set This mode is suitable for applications which calculate the average of the A D conversion result Table 9 5 Correspondence between Analog Input Pin and ADCRn Register 4 buffer mode timer trigger select 4 buffer Trigger Analog Input A D Conversion Results Register INTCC03 interrupt ANI0 to ANI3 ANI8 to ANI11 ADC...

Page 314: ...hot mode and less than the specified number of coincidence interrupts are generated the INTAD interrupt is not generated and the standby state is set if the CE bit is set to 1 This mode is suitable for applications which always monitor two or more analog inputs Table 9 6 Correspondence between Analog Input Pin and ADCRn Register scan mode timer trigger scan Trigger Analog Input A D Conversion Resu...

Page 315: ...g input Two select modes one buffer mode and four buffer mode are available for storing the conversion results 1 1 buffer mode External trigger select 1 buffer The A D converter converts one analog input using the ADTRG signal as a trigger The conversion results are stored in one ADCRn register refer to Table 9 7 Figure 9 12 The analog input and the A D conversion results register correspond one t...

Page 316: ... D CONVERTER Figure 9 12 Example of 1 Buffer Mode external trigger select 1 buffer Operation ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 ADTRG ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 A D Converter ...

Page 317: ...e for applications which calculate the average of the A D conversion result Table 9 8 Correspondence between Analog Input Pin and ADCRn Register 4 buffer mode external trigger select 4 buffer Trigger Analog Input A D Conversion Results Register ADTRG signal ANI0 to ANI3 ANI8 to ANI11 ADCR0 First time ADCR1 Second time ADCR2 Third time ADCR3 Fourth time ADTRG signal ANI4 to ANI7 ANI12 to ANI15 ADCR...

Page 318: ...D conversion is restarted every time a trigger is input from the ADTRG pin This mode is suitable for applications which always monitor two or more analog inputs Table 9 9 Correspondence between Analog Input Pin and ADCRn Register scan mode external trigger scan Trigger Analog Input A D Conversion Results Register ADTRG signal ANI0 ANI8 ADCR0 ADTRG signal ANI1 ANI9 ADCR1 ADTRG signal ANI2 ANI10 ADC...

Page 319: ...ion operations When canceled by NMI input the ADM0 ADM1 register and ADCRn register hold the value n 0 to 7 2 IDLE mode STOP mode As clock supply to the A D converter is stopped no conversion operations are performed When canceled using NMI input the ADM0 ADM1 register and the ADCRn register hold the value n 0 to 7 However when these modes are set during conversion conversion stops At this time if...

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Page 321: ...ansfers the data previously prepared in the PB register to the output latch by hardware simultaneously with the generation of CM10 coincidence interrupt of timer 1 and outputs it to external The pins to output the data to external are called a real time output port The real time output function can handle 8 bit real time output data Figure 10 1 shows the block diagram of the real time output port ...

Page 322: ... register can be read written in 8 or 1 bit units 10 3 Operation When the corresponding bit is set to the control mode by the PMC13 register the output pins can be used as a real time output port These pins can be accessed by the PB register and the RTP register The data is output by the following procedure 1 The data is written to the PB register 2 The contents of the PB register is transferred t...

Page 323: ...d the timing to change the output next are set refer to Figure 10 2 For the use of timer 1 refer to 7 2 2 Timer 1 Figure 10 2 Operational Timings of Real Time Output Port INTCM10 interrupt request 0H Timer 1 D01 D02 D03 D04 D00 D01 D02 D03 D00 D01 D02 D03 CM10 CM10 CM10 CM10 FFFFFFH Buffer register PB Output latch RTP Output pins RTP0 to RTP7 Hi Z Rewrites PB and CM10 in the interrupt processing r...

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Page 325: ...se configuration Main pulse 4 5 6 7 8 bits Additional pulse 8 bits Repeat frequency 129 kHz to 2 MHz fPWMC 33 MHz Pulse width overwrite frequency selection each one pulse 256 pulse Active level of the PWM output pulse can be selected Operation clock Can be selected from φ φ 2 φ 4 φ 8 and φ 16 φ is the internal system clock Remark n 0 to 3 ...

Page 326: ...ted by the SYNn bit of the PWMCn register for the reload timing PWM pulse width rewrite cycle 3 x bit down counter Controls the output timings of the main pulse The value of the modulo H register is loaded to this counter by the reload signal generated in the reload controls and decremented by PWM operational clock fPWMC Figure 11 1 Configuration of PWM Unit Remark n 0 to 3 x 4 to 8 specified with...

Page 327: ...nter main pulse PMPn2 PMPn1 PMPn0 Bit Length 0 0 0 8 bits 0 0 1 7 bits 0 1 0 6 bits 0 1 1 5 bits 1 0 0 4 bits Others Setting prohibited 2 SYNn Rewrite Cycle Specifies PWM pulse width rewrite cycle 0 Large cycle every PWM 2x 8 cycles 2x 8 fPWMC 1 Small cycle every PWM 1 cycle 2x fPWMC 1 PWMEn PWM Enable Controls operation stop of PWMn 0 Operation stops 1 Operation in progress PWM counter is cleared...

Page 328: ...its of the PWMCn register are 0 If the contents of this register are changed when the setting of the PWMEn bit is 1 the operation cannot be guaranteed Bit Position Bit Name Function 1 0 PWPn1 PWM Prescaler Clock Mode PWPn0 Selects operation clock of PWMn PWPn1 PWPn0 Operation Clock fPWMC 0 0 φ 0 1 φ 2 1 0 φ 4 1 1 φ 8 φ Internal system clock Remark n 0 to 3 Address FFFFF364H to FFFFF37CH 7 0 PWPRn ...

Page 329: ...PMPn bit set 0 to the rest of the higher bits 2 Modulo L register bit 0 to bit 7 The value of this register determines the additional timings of the additional pulse to perform minute adjustment refer to Figure 11 3 The value of this register becomes undefined by RESET input Set the data with initialization program before enabling PWM output The value from 0000H to FFFFH can be set to the PWMn reg...

Page 330: ...C 2x of the PWM clock fPWMC of φ to φ 4 set by the PWM prescaler register PWPR and the minimum pulse width is 1 fPWMC The PWM pulse output realizes 12 to 16 bit resolution by repeatedly outputting the PWM signal with 4 to 8 bit resolution and fPWMC 2x repeat frequency for 256 times The PWM pulse signal with 12 to 16 bit resolution is realized in 256 cycles by controlling the addition of the additi...

Page 331: ... level high level 0 Main pulse BRM additional pulse Modulo L 40H PWM output Main pulse PWMn xx40H PWMn xxC0H BRM additional pulse Modulo L C0H PWM output 1 2 3 4 5 6 7 8 9 10 11 12 13 254 255 1 fPWMC x 2x 1 fPWMC x Tx 1 fPWMC 16 bit resolution is gained when the 256 outputs are averaged 0 Main pulse L L L L BRM additional pulse Modulo L 00H PWM output Main pulse PWMn 0000H PWMn FFFFH BRM additiona...

Page 332: ...s generated In addition the value of the PWMn register is not loaded to the x bit down counter Therefore when the pulse width rewrite timing is set to 2x 8 large cycle SYN bit 0 operation starts in 2x 8 fPWMC max after the PWMEn bit is set The SYNn bit of the PWMCn register can be rewritten even during PWM output Initialize the following registers before starting PWMn operation PMC10 register Sett...

Page 333: ...ycle 2x fPWMC of the PWM pulse The specification of the PWM pulse width rewrite cycle is performed with the SYNn bit of the PWMCn register n 0 to 3 When the SYNn bit is cleared 0 the pulse width is changed at every 2 x 8 cycles 2 x 8 fPWMC of the PWM pulse Therefore it will take 2 x 8 clocks max before the pulse with the width corresponding to the data written to the PWMn register is output Figure...

Page 334: ...1 The pulse width is rewritten at every 1 cycle of the PWM pulse 2 The accuracy of the PWM pulse is x bits or more and x 8 bits or less Remarks 1 k l and m are the contents of the PWMn register 2 n 0 to 3 PWM pulse width rewrite timing PWM pulse width rewrite timing PWM pulse width rewrite timing Enables PWM output m l Rewrites PWMn register PWM pulse 2 x 8 cycles Contents of PWMn register PWMn ou...

Page 335: ...ulse Repetition Frequency Pulse Width Rewrite Cycle Large Cycle SYNn bit 0 Small Cycle SYNn bit 1 4 bits 8 bits fPWMC 16 fPWMC 212 fPWMC 24 5 bits 8 bits fPWMC 32 fPWMC 213 fPWMC 25 6 bits 8 bits fPWMC 64 fPWMC 214 fPWMC 26 7 bits 8 bits fPWMC 128 fPWMC 215 fPWMC 27 8 bits 8 bits fPWMC 256 fPWMC 216 fPWMC 28 fPWMC Select from φ φ 2 φ 4 and φ 8 by the PWPRn register ...

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Page 337: ...00 337 CHAPTER 12 PORT FUNCTION 12 1 Features The ports of the V854 have the following features Number of pins input 16 I O 96 Also function as I O pins of other peripheral functions Can be set in input output mode in 1 bit units ...

Page 338: ...ake up ports 0 to 14 The configuration of the V854 s ports is shown below P20 cannot be used for a port function Port 0 P00 to P07 Port 1 P10 to P17 Port 2 P20 P21 to P26 Port 3 P30 to P36 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P60 to P67 Port 7 Port 8 P70 to P77 P80 to P87 Port 9 P90 to P96 Port 10 Port 11 P100 to P103 P110 to P117 Port 12 P120 to P127 Port 13 P130 to P137 Port 14 P140 to P14...

Page 339: ... C P36 is only for port Port 4 P40 to P47 8 bit I O Address data bus for external memory Port 5 P50 to P57 Port 6 P60 to P67 8 bit I O Address bus for external memory Port 7 P70 to P77 8 bit input Analog input to A D converter only for input in the port mode Port 8 P80 to P87 Port 9 P90 to P96 7 bit I O Control signal input output for external memory Port 10 P100 to P103 4 bit I O PWM control sign...

Page 340: ...TP12 P12 input P13 INTP13 P13 input P14 INTP14 TI1 P14 input P15 TO20 P15 input P16 INTP20 TI20 P16 input P17 P17 input Port 2 P20 NMI NMI input P21 INTP30 P21 input PMC2 P22 ADTRG P22 input P23 INTP50 P23 input P24 INTP51 P24 input P25 INTP52 P25 input P26 INTP53 P26 input Port 3 P30 SO0 TDX P30 input PMC3 P31 SI0 RXD P31 input P32 SCK0 P32 input P33 SO1 SDA P33 input P34 SI1 P34 input P35 SCK1 S...

Page 341: ...put ASTB output P95 HLDAK P95 input P96 HLDRQ P96 input Port 10 P100 PWM0 P100 input PMC10 P101 PWM1 P101 input P102 PWM2 P102 input P103 PWM3 P103 input Port 11 P110 TO21 P110 input PMC11 P111 INTP21 TI21 P111 input P112 TO22 P112 input P113 INTP22 TI22 P113 input P114 TO23 P114 input P115 INTP23 TI23 P115 input P116 TO24 P116 input P117 INTP24 TI24 P117 input Port 12 P120 SO2 P120 input PMC12 P1...

Page 342: ...igure 12 2 Block Diagram of Type B Remark m port number n bit number WRPMC WRPM PMCmn PMmn Pmn WRPORT RDIN Address Output signal in control mode Pmn Selector Selector Selector Internal bus WRPMC WRPM PMCmn PMmn Pmn WRPORT RDIN Pmn Selector Selector Internal bus Input signal in control mode Noise elimination Edge detection Address ...

Page 343: ... Figure 12 4 Block Diagram of Type D Remark m port number n bit number WRPMC WRPM PMCmn PMmn Pmn WRPORT RDIN Pmn Selector Selector Internal bus Input signal in control mode Address Output signal in control mode Selector WRPMC WRPM PMCmn PMmn Pmn WRPORT RDIN Pmn Selector Selector Internal bus Input signal in control mode Address ...

Page 344: ...rt number n bit number Internal bus PMmn Pmn Selector Selector Selector RDIN Address WRPORT WRPM Output signal in control mode Pmn Input signal in control mode Input output control circuit MODE0 to MODE2 MM0 to MM2 Internal bus PMmn Pmn Selector Selector Selector RDIN Address WRPORT WRPM Output signal in control mode Pmn Input output control circuit MODE0 to MODE2 MM0 to MM2 ...

Page 345: ... of Type G Remark m 7 8 n 0 to 7 Figure 12 8 Block Diagram of Type H Internal bus RDIN Pmn ANI0 to ANI15 Input signal in control mode Internal bus PM96 P96 Selector Selector RDIN Address WRPORT WRPM P96 Input output control circuit MM0 to MM2 MODE0 to MODE2 Input signal in control mode ...

Page 346: ...ION Figure 12 9 Block Diagram of Type I Figure 12 10 Block Diagram of Type J Remark m port number n bit number WRPM PMmn Pmn WRPORT RDIN Address Pmn Selector Selector Internal bus Internal bus RDIN P20 1 Address NMI Noise elimination Edge detection Selector ...

Page 347: ... 12 PORT FUNCTION Figure 12 11 Block Diagram of Type K Remark m port number n bit number WRPMC WRPM PMCmn PMmn Pmn WRPORT RDIN Pmn N ch Selector Selector Internal bus Input signal in control mode Address Output signal in control mode Selector ...

Page 348: ...o be used to input output signals of the real time pulse unit RPU and input external interrupt requests when placed in the control mode 1 Operations in control mode Port Control Mode Function in Control Mode Block Type Port 0 P00 TO00 RPU output A P01 TO01 P02 INTP00 External interrupt request input RPU capture trigger input B P03 INTP01 P04 INTP02 P05 INTP03 P06 TCLR0 INTP04 External interrupt re...

Page 349: ...ort mode Control Specifies operation mode of P07 pin 0 I O port mode 1 External interrupt request input INTP05 TI0 input mode 6 PMC06 Port Mode Control Specifies operation mode of P06 pin 0 I O port mode 1 External interrupt request input INTP04 TCLR0 input mode 5 to 2 PMC05 to Port Mode Control PMC02 Specifies operation mode of P05 to P02 pins 0 I O port mode 1 External interrupt request input IN...

Page 350: ...nals of the real time pulse unit RPU and to input external interrupts when placed in the control mode 1 Operations in control mode Port Control Mode Function in Control Mode Block Type Port 1 P10 INTP10 External interrupt request input RPU capture trigger input B P11 INTP11 P12 INTP12 P13 INTP13 P14 TI1 INTP14 External interrupt request input P15 TO20 RPU output A P16 TI20 INTP20 External interrup...

Page 351: ...d ignored when 1 is written Bit Position Bit Name Function 6 PMC16 Port Mode Control Specifies operation mode of P16 pin 0 I O port mode 1 External interrupt request input INTP20 TI20 input mode 5 PMC15 Port Mode Control Specifies operation mode of P15 pin 0 I O port mode 1 TO20 output mode 4 PMC14 Port Mode Control Specifies operation mode of P14 pin 0 I O port mode 1 External interrupt request i...

Page 352: ...rupt request input when placed in the control mode When port 2 is accessed in 8 bit units for write the data in the higher 1 bit is ignored When it is accessed in 8 bit units for read undefined data is read 1 Operations in control mode Port Control Mode Function in Control Mode Block Type Port 2 P20 NMI Non maskable interrupt request input I P21 INTP30 External interrupt request input capture trig...

Page 353: ...C2 This register can be read written in 8 or 1 bit units However bit 0 is fixed to 1 by hardware and ignored when 0 is written Bit 7 is fixed to 0 by hardware and ignored when 1 is written Bit Position Bit Name Function 6 to 3 PMC26 to Port Mode Control PMC23 Sets operation mode of P26 to P23 pins 0 I O port mode 1 External interrupt request input INTP53 to INTP50 2 PMC22 Port Mode Control Sets op...

Page 354: ...he control mode P33 and P35 are multiplexed with SDA and SCL pin of I2 C bus respectively and output is N ch open drain When port 3 is accessed in 8 bit units for write the data in the higher 1 bit is ignored When it is accessed in 8 bit units for read undefined data is read 1 Operations in control mode Port Control Mode Function in Control Mode Block Type Port 3 P30 SO0 TXD Serial interface I O U...

Page 355: ...rol mode is set by port mode control register 3 PMC3 Port 3 mode register PM3 This register can be read written in 8 or 1 bit units Bit Position Bit Name Function 6 to 0 PM3n Port Mode n 6 to 1 Sets P3n pin in input output mode 0 Output mode output buffer ON 1 Input mode output buffer OFF 7 1 PM3 6 PM36 5 PM35 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30 Address FFFFF026H After reset FFH ...

Page 356: ...e 4 PMC34 Port Mode Control Sets operation mode of P34 pin 0 I O port mode 1 SI1 input mode 3 PMC33 Port Mode Control Sets operation mode of P33 pin 0 I O port mode 1 SO1 SDA output mode 2 PMC32 Port Mode Control Sets operation mode of P32 pin 0 I O port mode 1 SCK0 I O mode 1 PMC31 Port Mode Control Sets operation mode of P31 pin 0 I O port mode 1 SI0 RXD input mode 0 PMC30 Port Mode Control Sets...

Page 357: ...ort In addition to the function as a general I O port this port also serves as an external address data bus for external memory expansion when placed in the control mode external expansion mode 1 Operation in control mode Port Control Mode Function in Control Mode Block Type Port 4 P40 to P47 AD0 to AD7 Address data bus for external memory E 7 P47 P4 6 P46 5 P45 4 P44 3 P43 2 P42 1 P41 0 P40 Addre...

Page 358: ...t buffer ON 1 Input mode output buffer OFF Operation mode of port 4 Bit of MM Register Operation Mode MM2 MM1 MM0 P40 P41 P42 P43 P44 P45 P46 P47 0 0 0 Port 0 1 1 1 0 0 Address data bus 1 0 1 AD0 to AD7 1 1 1 Others RFU reserved For the details of mode selection by the MODE pins refer to 3 3 2 Specifying operation mode In the ROM less mode MM0 to MM2 bits are initialized to 111 at system reset ena...

Page 359: ...rt In addition to the function as a general I O port this port also serves as an external address data bus for external memory expansion when placed in the control mode external expansion mode 1 Operation in control mode Port Control Mode Function in Control Mode Block Type Port 5 P50 to P57 AD8 to AD15 Address data bus for external memory E 7 P57 P5 6 P56 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 Addre...

Page 360: ...Port 5 mode register PM5 This register can be read written in 8 or 1 bit units Bit Position Bit Name Function 7 to 0 PM5n Port Mode n 7 to 0 Sets P5n pin in input output mode 0 Output mode output buffer ON 1 Input mode output buffer OFF Operation mode of port 5 Bit of MM Register Operation Mode MM2 MM1 MM0 P50 P51 P52 P53 P54 P55 P56 P57 0 0 0 Port 0 1 1 1 0 0 Address data bus 1 0 1 AD8 to AD15 1 ...

Page 361: ...ort In addition to the function as a general I O port this port also serves as an external address bus for external memory expansion when placed in the control mode external expansion mode 1 Operation in control mode Port Control Mode Function in Control Mode Block Type Port 6 P60 to P67 A16 to A23 Address bus for external memory expansion F Address FFFFF00CH 7 P67 P6 6 P66 5 P65 4 P64 3 P63 2 P62...

Page 362: ... 6 mode register PM6 This register can be read written in 8 or 1 bit units Bit Position Bit Name Function 7 to 0 PM6n Port Mode n 7 to 0 Sets P6n pin in input output mode 0 Output mode output buffer ON 1 Input mode output buffer OFF Operation mode of port 6 Bit of MM Register Operation Mode MM2 MM1 MM0 P60 P61 P62 P63 P64 P65 P66 P67 0 0 0 Port 0 1 1 1 0 0 A16 A17 1 0 1 A18 A19 1 1 0 A20 A21 1 1 1...

Page 363: ...nalog input pins ANI0 to ANI7 and ANI8 to ANI15 but the input port and analog input pin cannot be switched The status of each pin can be read by reading out ports 1 Normal operation Port Control Mode Function in Control Mode Block Type Port 7 P70 to P77 ANI0 to ANI7 Analog input to A D converter G Port 8 P80 to P87 ANI8 to ANI15 only for input in port mode Address FFFFF00EH 7 P77 P7 6 P76 5 P75 4 ...

Page 364: ...trol signals when placed in the control mode external expansion mode When port 9 is accessed in 8 bit units for write the higher 1 bit is ignored When it is accessed in 8 bit units for read undefined data is read 1 Operations in control mode Port Control Mode Function in Control Mode Block Type Port 9 P90 LBEN WRL Control signal output for external memory F P91 UBEN P92 R W WRH P93 DSTB RD P94 AST...

Page 365: ...owever bit 7 is ignored during write access and undefined during read access Bit Position Bit Name Function 6 to 0 PM9n Port Mode n 6 to 0 Sets P9n pin in input output mode 0 Output mode output buffer ON 1 Input mode output buffer OFF Operation mode of port 9 P90 to P94 P95 P96 Bit of MM Register Operation Mode MM3 Operation Mode P95 P96 MM2 MM1 MM0 P90 P91 P92 P93 P94 0 Port mode Port 0 0 0 Port ...

Page 366: ...in 8 bit units for write the data in the higher 4 bits is ignored When it is accessed in 8 bit units for read undefined data is read In addition to the function as a general I O port this port can also be used to output the PWMn 1 Operations in control mode Port Control Mode Function in Control Mode Block Type Port 10 P100 PWM0 PWM control signal output A P101 PWM1 P102 PWM2 P103 PWM3 Address FFFF...

Page 367: ...t Name Function 3 to 0 PM10n Port Mode n 3 to 0 Sets P10n pin in input output mode 0 Output mode output buffer ON 1 Input mode output buffer OFF Port 10 mode control register PMC10 This port can be read written in 8 or 1 bit units However the higher 4 bits are fixed to 0 and ignored if 1 is written in Bit Position Bit Name Function 3 to 0 PMC10n Port Mode Control n 3 to 0 Sets operation mode of P1...

Page 368: ...nterrupt requests when placed in the control mode 1 Operations in control mode Port Alternate Function Function in Control Mode Block Type Port 11 P110 TO21 RPU output A P111 TI21 INTP21 RPU input external interrupt request input B P112 TO22 RPU output A P113 TI22 INTP22 RPU input external interrupt request input B P114 TO23 RPU output A P115 TI23 INTP23 RPU input external interrupt request input ...

Page 369: ...e is set by port mode control register 11 PMC11 Port 11 mode register PM11 This register can be read written in 8 or 1 bit units Bit Position Bit Name Function 7 to 0 PM11n Port Mode n 7 to 0 Sets P11n pin in input output mode 0 Output mode output buffer ON 1 Input mode output buffer OFF Address FFFFF036H 7 PM117 PM11 6 PM116 5 PM115 4 PM114 3 PM113 2 PM112 1 PM111 0 PM110 After reset FFH ...

Page 370: ... request input INTP23 TI23 input mode 4 PMC114 Port Mode Control Sets P114 pin in input output mode 0 I O port mode 1 TO23 output mode 3 PMC113 Port Mode Control Sets P113 pin in input output mode 0 I O port mode 1 External interrupt request input INTP22 TI22 input mode 2 PMC112 Port Mode Control Sets P112 pin in input output mode 0 I O port mode 1 TO22 output mode 1 PMC111 Port Mode Control Sets ...

Page 371: ...output C P123 SO3 Serial interface output A P124 SI3 Serial interface input D P125 SCK3 Serial interface output C P126 Only for port J P127 CLO Clock output A 2 Setting input output mode and control mode The input output mode of port 12 is set by the port mode register 12 PM12 The control mode is set by the port mode control register 12 PMC12 Port 12 mode register PM12 This register can be read wr...

Page 372: ...e 1 SCK3 input output mode 4 PMC124 Port Mode Control Sets P124 pin in input output mode 0 I O port mode 1 SI3 input mode 3 PMC123 Port Mode Control Sets P123 pin in input output mode 0 I O port mode 1 SO3 output mode 2 PMC122 Port Mode Control Sets P122 pin in input output mode 0 I O port mode 1 SCK2 input output mode 1 PMC121 Port Mode Control Sets P121 pin in input output mode 0 I O port mode 1...

Page 373: ...nction 7 to 0 P13n Port 13 n 7 to 0 I O port In addition to the function as a port this port can also be used as the output of real time output port 1 Operation in control mode Port Alternate Function Pin Function in Control Mode Block Type Port 13 P130 to P137 RTP0 to RTP7 Real time output port A Address FFFFF01AH 7 P137 P13 6 P136 5 P135 4 P134 3 P133 2 P132 1 P131 0 P130 After reset Undefined ...

Page 374: ...ol register PMC13 This register can be read written in 8 or 1 bit units Bit Position Bit Name Function 7 to 0 PMC13n Port Mode Control n 7 to 0 Sets P13n pin in input output mode 0 I O port mode 1 RTPn output mode Caution When each bit is set to 1 the output buffer of the corresponding port is turned on regardless of the contents of the PM13 register and the contents of the RTP register are output...

Page 375: ... control mode The input output mode of port 14 is set by port mode register 14 PM14 Port 14 does not have port mode control register 14 PMC14 because it is not provided with the control mode Port 14 mode register PM14 This register can be read written in 8 or 1 bit units Bit Position Bit Name Function 7 to 0 PM14n Port Mode n 7 to 0 Sets P14n pin in input output mode 0 Output mode output buffer ON...

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Page 377: ...S CVDD CVSS AVDD AVSS and AVREF pins are in the high impedance state When an external memory is connected a pull up or pull down resistor must be connected to each pin of ports 4 5 6 and 9 Otherwise the memory contents may be lost if these pins go into a high impedance state Also treat signal outputs of the on chip peripheral I O function and the output port so that they will not be affected In th...

Page 378: ...to AD15 A16 to A23 Port mode Hi Z LBEN P90 Hi Z WRL WRL P90 LBEN Hi Z UBEN P91 Hi Z R W P92 Hi Z WRH WRH P92 R W Hi Z DSTB P93 Hi Z RD RD P93 DSTB Hi Z ASTB P94 Hi Z HLDAK Port mode CLKOUT L Operates L SO0 SO2 TXD Port mode Operation TO00 TO01 TO20 to TO24 RTP0 to RTP7 Port mode Hi Z SDA SDL SO1 SO3 PWM0 to PWM3 Remark Hi Z High impedance L Low level output 1 Accepting reset signal Note The intern...

Page 379: ...lation stabilization time when an external clock is used in the direct mode 13 3 Initialize Table 13 2 shows the initial value of each register after reset The contents of the registers must be initialized in the program as necessary Especially set the following registers as necessary because they are related to system setting Power save control register PSC X1 and X2 pin function CLKOUT pin opera...

Page 380: ...ister CLOM 00H Real time pulse unit Timer control register TMC01 TMC02 00H TMC00 TMC1 TMC20 to TMC24 TMC3 01H Timer output control register TOC0 TOC1 00H Capture compare register Undefined CC00 to CC03 CC00L to CC03L CC3 Compare register CM10 CM11 CM10L CM11L CM20 to CM24 Undefined Capture register CP10 to CP13 CP10L to CP13L CP3 Undefined Timer register TM0 TM1 TM0L TM1L TM20 to TM24 TM3 0000H Ti...

Page 381: ... selection register IICCL 00H IIC shift register IIC 00H Slave address register SVA 00H PWM PWM control register PWMC0 to PWMC3 05H PWM prescaler register PWPR0 to PWPR3 00H PWM modulo register PWM0 to PWM3 Undefined Interrupt exception processing function Interrupt control register xxICn 47H In service priority register ISPR 00H External interrupt mode register INTM0 to INTM7 00H Event divide cou...

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Page 383: ...de easier by differentiating software Data adjustment in starting mass production is made easier 14 1 Features 4 byte 1 clock access in instruction fetch access All area one shot erase Communication through serial interface from the dedicated flash writer Erase writing voltage VPP 7 8 V On board programming Number of rewrite 100 times target 14 2 Writing by Flash Writer Writing can be performed ei...

Page 384: ...programs to the flash memory of the V854 A host machine is required for controlling the dedicated flash writer UART or CSI is used as the interface between the dedicated flash writer and the V854 to perform writing erasing etc A dedicated program adapter FA Series is required for off board writing RS 232C Host machine Dedicated flash writer VPP VDD VSS RESET UART CSI0 V854 ...

Page 385: ...t 2 CSI0 Transfer rate up to 8 25 Mbps MSB first The dedicated flash writer outputs the transfer clock and the V854 operates as a slave When Flashpro II is used as the dedicated flash writer it generates the following signals to the V854 For the details refer to the Flashpro II manual Remark Flashpro II is a product of Naitou Densei Machidaseisakusho Co Ltd Dedicated flash writer V854 VPP VDD VSS ...

Page 386: ...voltage VPP VDD I O VDD voltage generation VDD voltage monitoring GND Ground VSS CLK Output Clock output to V854 X1Note RESET Output Reset signal RESET SI RXD Input Receive signal SO0 TXD SO TXD Output Transmit signal SI0 RXD SCK Output Transfer clock SCK0 x Note Only for off board writing Remark Always connected Does not need to connect if generated on the target board x Does not need to connect ...

Page 387: ...ng mode all the pins not used for the flash memory programming become the same status as that immediately after reset of single chip mode 1 Therefore all the ports become high impedance status so that pin handling is required when the external device does not acknowledge the high impedance status 14 5 1 VPP pin In the normal operation mode 0 V is input to VPP pin In the flash memory programming mo...

Page 388: ...f other devices etc 1 Conflict of signals When connecting a dedicated flash writer output to a serial interface pin input which is connected to another device output conflict of signals occurs To avoid the conflict of signals isolate the connection to the other device or set the other device to the high impedance status Input pin Dedicated flash writer connection pin Conflict of signals Output pin...

Page 389: ... the connection to the other device or make the setting so that the input signal to the other device is ignored Pin Dedicated flash writer connection pin Input pin The other device V854 Pin Dedicated flash writer connection pin Input pin The other device V854 In the flash memory programming mode if the signal the V854 outputs affects the other device isolate the signal on the other device side In ...

Page 390: ...voltage to VPP pin and release the reset 14 5 6 Port pin When the flash memory programming mode is set all the port pins except the pins which communicate with the dedicated flash writer become output high impedance status The treatment of these port pins are not necessary If problems such as disabling output high impedance status should occurs to the external devices connected to the port connect...

Page 391: ...Y ONLY 14 6 Programming Method 14 6 1 Flash memory control The following shows the procedure that this firmware manipulates the flash memory Starts Switches to flash memory programming mode Selects communication system Manipulates flash memory Ends Yes No Ends Supplies RESET pulse ...

Page 392: ...ther than the above Setting prohibited 14 6 3 Selection of communication mode In the V854 a communication system is selected by inputting pulse 16 pulses max to VPP pin after switching to the flash memory programming mode The VPP pulse is generated by the dedicated flash writer The following shows the relation between the number of pulses and the communication systems Table 14 1 List of Communicat...

Page 393: ...he address following the high speed write command executed immediately before and executes verify check System setting and control Status read out command Acquires the status of operations Oscillating frequency setting command Sets the oscillating frequency Erasing time setting command Sets the erasing time of one shot erase Writing time setting command Sets the writing time of data write Baud rat...

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Page 395: ...r F in the product names Part Number µPD703006 µPD703008 703008Y µPD70F3008 70F3008Y Parameter On chip ROM None Mask ROM Flash memory Flash memory programming pin None Provided VPP Flash memory programming mode None Provided VPP 7 8 V MODE0 to MODE2 High level Electrical specifications Current consumption etc differ Refer to each product data sheet Others Noise immunity and noise radiation differ ...

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Page 397: ...scaler mode register 0 BRG 292 BPRM1 Baud rate generator prescaler mode register 1 BRG 292 BPRM2 Baud rate generator prescaler mode register 2 BRG 292 BPRM3 Baud rate generator prescaler mode register 3 BRG 292 BRGC0 Baud rate generator compare register 0 BRG 291 BRGC1 Baud rate generator compare register 1 BRG 291 BRGC2 Baud rate generator compare register 2 BRG 291 BRGC3 Baud rate generator comp...

Page 398: ...Capture register 10 RPU 162 CP10L Capture register 10L RPU 162 CP11 Capture register 11 RPU 162 CP11L Capture register 11L RPU 162 CP12 Capture register 12 RPU 162 CP12L Capture register 12L RPU 162 CP13 Capture register 13 RPU 162 CP13L Capture register 13L RPU 162 CP3 Capture register 3 RPU 165 CSIC0 Interrupt control register INTC 116 CSIC1 Interrupt control register INTC 116 CSIC2 Interrupt co...

Page 399: ...0 INTC 106 INTM1 External interrupt mode register 1 INTC 121 INTM2 External interrupt mode register 2 INTC 121 INTM3 External interrupt mode register 3 INTC 121 INTM4 External interrupt mode register 4 INTC 121 INTM5 External interrupt mode register 5 INTC 121 INTM6 External interrupt mode register 6 INTC 121 INTM7 External interrupt mode register 7 INTC 123 ISPR In service priority register INTC ...

Page 400: ...r Port 365 PM10 Port 10 mode register Port 367 PM11 Port 11 mode register Port 369 PM12 Port 12 mode register Port 371 PM13 Port 13 mode register Port 374 PM14 Port 14 mode register Port 375 PMC0 Port 0 mode control register Port 349 PMC1 Port 1 mode control register Port 351 PMC2 Port 2 mode control register Port 353 PMC3 Port 3 mode control register Port 356 PMC10 Port 10 mode control register P...

Page 401: ...Interrupt control register INTC 116 SVA I2 C slave address register I2 C 242 SYC System control register BCU 82 SYS System status register CG 79 139 TM0 Timer 0 RPU 161 TM0L Timer 0L RPU 161 TM1 Timer 1 RPU 162 TM1L Timer 1L RPU 162 TM20 Timer 20 RPU 164 TM21 Timer 21 RPU 164 TM22 Timer 22 RPU 164 TM23 Timer 23 RPU 164 TM24 Timer 24 RPU 164 TM3 Timer 3 RPU 165 TMC00 Timer control register 00 RPU 1...

Page 402: ...anual U11969EJ3V0UM00 APPENDIX A REGISTER INDEX 6 6 Symbol Name Unit Page TOVS Timer overflow status register RPU 173 TXS Transmit shift register 9 bits UART 214 TXSL Transmit shift register L lower 8 bits UART 214 ...

Page 403: ...ption Symbol Description Assignment GR General register SR System register zero extend n Zero extends n to word length sign extend n Sign extends n to word length load memory a b Reads data of size b from address a store memory a b c Writes data b of size c to address a load memory bit a b Reads bit b of address a store memory bit a b c Writes c to bit b of address a saturated n Performs saturated...

Page 404: ...on Blank Not affected 0 Cleared to 0 1 Set to 1 x Set or cleared according to result R Previously saved value is restored Condition code V 0 0 0 0 OV 1 Overflow NV 1 0 0 0 OV 0 No overflow C L 0 0 0 1 CY 1 Carry Lower Less than NC NL 1 0 0 1 CY 0 No carry No lower Greater than or equal Z E 0 0 1 0 Z 1 Zero Equal NZ NE 1 0 1 0 Z 0 Not zero Not equal NH 0 0 1 1 CY or Z 1 Not higher Less than or equa...

Page 405: ... memory adr Byte LD H disp16 reg1 reg2 adr GR reg1 sign extend disp16 1 1 2 GR reg2 sign extend Load memory adr Halfword LD W disp16 reg1 reg2 adr GR reg1 sign extend disp16 1 1 2 GR reg2 Load memory adr Word Notes 1 dddddddd is the higher 8 bits of disp9 2 Only the lower half word is valid 3 ddddddddddddddddddddd is the higher 21 bits of disp22 4 ddddddddddddddd is the higher 15 bits of disp16 Op...

Page 406: ...PC FEPC PSW FEPSW else PC EIPC PSW EIPSW SAR reg1 reg2 GR reg2 GR reg2 arithmetically shift right 1 1 1 x 0 x x by GR reg1 imm5 reg2 GR reg2 GR reg2 arithmetically shift right 1 1 1 x 0 x x by zero extend imm5 Notes 1 The op code of this instruction uses the field of reg1 though the source register is shown as reg2 in the above table Therefore the meaning of register specification for mnemonic des...

Page 407: ...p8 ep reg2 adr ep zero extend disp8 1 1 2 GR reg2 sign extend Load memory adr Halfword SLD W disp8 ep reg2 adr ep zero extend disp8 1 1 2 GR reg2 Load memory adr Word SST B reg2 disp7 ep adr ep zero extend disp7 1 1 1 Store memory adr GR reg2 Byte SST H reg2 disp8 ep adr ep zero extend disp8 1 1 1 Store memory adr GR reg2 Halfword SST W reg2 disp8 ep adr ep zero extend disp8 1 1 1 Store memory adr...

Page 408: ... reg2 result GR reg2 AND GR reg1 1 1 1 0 x x TST1 bit 3 disp16 reg1 adr GR reg1 sign extend disp16 3 3 3 x Z flag Not Load memory bit adr bit 3 XOR reg1 reg2 GR reg2 GR reg2 XOR GR reg1 1 1 1 0 x x XORI imm16 reg1 reg2 GR reg2 GR reg1 XOR zero extend imm16 1 1 1 0 x x Note ddddddddddddddd is the higher 15 bits of disp16 Operation Operand Code r r r r r 1 1 10 1 1RRRRR d dd d dd d dd d dd d dd 0 No...

Page 409: ...VSS 45 B baud rate generator 0 to 3 286 baud rate generator compare register 0 to 3 291 baud rate generator prescaler mode register 0 to 3 292 baud rate generators 0 to 3 set up values 289 BCC 88 BCn1 n 0 to 7 88 BCU 29 BIC 82 block diagram of ports 342 BPRM0 to BPRM3 292 BPRn0 to BPRn3 n 0 to 3 292 BRCE0 to BRCE3 292 BRGC0 to BRGC3 291 BRGn0 to BRGn7 n 0 to 3 291 BS 297 buffer register 322 bus ac...

Page 410: ...o CM2MK4 116 CM2PRn0 to CM2PRn2 n 0 to 4 116 CMS00 to CMS03 167 CMS3 171 COI 239 command register 78 communication command 393 communication reservation 273 compare operation timer 0 181 compare operation timer 1 187 compare operation timer 2 189 compare operation timer 3 194 compare register 10 11 163 compare register 20 to 24 164 conflict of signals 388 count clock selection timer 0 175 count cl...

Page 411: ...external interrupt mode register 7 123 external memory area 65 external wait function 87 external trigger mode 302 315 F FE 212 FECC 52 FEPC 52 FEPSW 52 flash memory 383 flash memory programming mode 54 392 FR0 to FR2 299 frequency divider 124 FS0 to FS2 154 function block configuration 28 G general register 51 global pointer 51 H halfword access 84 HALT mode 140 143 HLDAK 42 HLDRQ 42 I I O circui...

Page 412: ...TSER 215 INTSR 215 INTST 215 ISPR 118 ISPR0 to ISPR7 118 L LBEN 41 link pointer 51 LREL 237 LV 154 M maskable interrupt 107 maskable interrupt status flag 118 measurement of cycle 201 measurement of pulse width 196 memory block function 85 memory boundary operation condition 97 memory expansion mode register 68 memory map 59 memory read 90 memory write 94 MM 68 MM0 to MM3 68 MOD0 to MOD3 222 MODE0...

Page 413: ...1 P60 to P67 40 361 P7 363 P70 to P77 40 363 P8 368 P80 to P87 40 368 P9 364 P90 to P96 41 364 PALV0 to PALV3 327 PB 322 PC 51 PE 212 period in which interrupt is not acknowledged 133 peripheral I O area 63 peripheral I O register 71 pin configuration 26 pin function 31 37 pin status 36 PLL lock up 139 PLL mode 136 PLLSEL 44 PM0 349 PM00 to PM07 349 PM1 351 PM10 register 367 PM10 to PM17 bit 351 P...

Page 414: ...ster 365 Port 10 mode register 367 Port 11 mode register 369 Port 12 mode register 371 Port 13 mode register 374 Port 14 mode register 375 power save control 140 power save control register 142 PRCMD 78 PRERR 79 139 PRM00 to PRM03 166 PRM10 to PRM13 169 PRM2n0 to PRM2n4 n 0 to 4 170 PRM30 to PRM33 171 program counter 51 program register set 51 program space 58 69 97 program status word 53 programm...

Page 415: ... SPIE 237 SPT 238 SRIC0 116 SRIF0 116 SRMK0 116 SRPR00 to SRPR02 116 stack pointer 51 start condition 243 status saving register for interrupt 54 status saving register for NMI 52 STD 240 STIC0 116 STIF0 116 STMK0 116 stop condition 247 STP 142 STPR00 to STPR02 116 STT 238 SVA 242 SYC 82 SYN0 to SYN3 327 SYS 79 139 system control register 82 system register set 52 system status register 79 T TBC 1...

Page 416: ...02 168 TMC1 169 TMC20 to TMC24 170 TMC3 171 TO00 TO01 37 TO20 37 TO21 to TO24 43 TOC0 TOC1 172 toggle output 191 TOVS 173 transmission completion interrupt 215 transmission shift register 214 TRAP0n TRAP1n n 0 to F 100 TRC 240 TRG0 TRG1 299 TXD 38 TXE 209 TXED 214 TXS TXSL 214 TXS0 to TXS7 214 U UART 206 UBEN 41 UNLOCK 79 139 V VDD 45 VPP 46 VSS 45 W WAIT 44 Wake up function 273 Wait function 86 W...

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