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User’s Manual U11969EJ3V0UM00
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 5-5. Maskable Interrupt Processing
The INT input masked by the interrupt controllers and the INT input that occurs while the other interrupt is being
processed (when PSW.NP = 1 or PSW.ID = 1) are internally pended by the interrupt controller. When the interrupts
are unmasked, or when PSW.NP = 0 and PSW.ID = 0 by using the RETI and LDSR instructions, the pending INT
input starts the new maskable interrupt processing.
Maskable interrupt request
Interrupt processing
EIPC
EIPSW
ECR. EICC
PSW. EP
PSW. ID
PC
←
←
←
INTC accepted
CPU processing
XXIF = 1
No
Yes
XXMK = 0
Priority higher than
that of interrupt currently
processed?
Interrupt request pending
PSW. NP
PSW. ID
Interrupt process pending
No
No
No
No
1
0
1
0
Interrupt request?
INT input
Yes
Yes
Yes
Yes
Priority higher
than that of other interrupt
request?
Highest default
priority of interrupt requests
with same priority?
Interrupt unmasked?
restored PC
PSW
exception code
0
1
vector address
←
←
←
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