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User’s Manual U11969EJ3V0UM00
133
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.7 Interrupt Response Time
Interrupt Response Time from the interrupt request generation to the interrupt processing activation is as follows:
Figure 5-14. Pipeline Operation at Interrupt Request Acknowledge (General Description)
INT1 to INT4 : interrupt acknowledge processing
IFx
: invalid instruction fetch
IDx
: invalid instruction decode
Interrupt Response Time (internal system clock)
Condition
Internal interrupt
External interrupt
Minimum
11
13
Except the condition below:
• In IDLE/software STOP mode
Maximum
18
20
• External bus is accessed
• Two or more interrupt request non-sample instructions are executed in
succession
• Access to interrupt control register
5.8 Periods Where Interrupt is Not Acknowledged
An interrupt request is acknowledged while an instruction is being executed. However, no interrupt request will
be acknowledged between an interrupt request non-sample instruction and the next instruction.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (vs. PSW)
In the following conditions, an interrupt may not be acknowledged.
(1) Immediately after the RETI instruction execution
(2) Immediately after the data write to the following registers.
• Interrupt control register (xxICn)
• Command register (PRCMD)
• In-service priority register (ISPR)
Internal system clock
(CLKOUt output)
IF
ID
IFx IDx
IFx
EX MEM
INT1 INT2 INT3
IF
ID
EX MEM WB
INT4
WB
Interrupt request
Instruction 1
Instruction 2
Instruction 3
Interrupt acknowledge operation
Instruction (start instruction of
interrupt processing routine)
7 to 14 system clocks
4 system clocks
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