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User’s Manual U11969EJ3V0UM00
CHAPTER 4 BUS CONTROL FUNCTION
4.5 Wait Function
4.5.1 Programmable wait function
To facilitate interfacing with low-speed memories and I/O devices, up to 3 data wait states can be inserted in a
bus cycle for two memory blocks. The number of wait states can be programmed by using data wait control register
(DWC). Immediately after the system has been reset, three data wait states are automatically programmed for all
memory blocks.
(1) Data wait control register (DWC)
This register can be read/written in 16-bit units.
Bit Position
Bit Name
Function
15 to 0
DWn1
Data Wait
DWn0
Specifies number of wait states to be inserted
(n = 0 to 7)
DWn1
DWn0
Number of wait states to be inserted
0
0
0
0
1
1
1
0
2
1
1
3
n
Blocks into which wait states are inserted
0
Blocks 0/1
1
Blocks 2/3
2
Blocks 4/5
3
Blocks 6/7
4
Blocks 8/9
5
Blocks 10/11
6
Blocks 12/13
7
Blocks 14/15
Cautions 1. Block 0 is reserved for the internal ROM area in the single-chip mode. It is not subject
to programmable wait control, regardless of the setting of DWC, and is always accessed
without wait states.
2. The internal RAM area of block 15 is not subject to programmable wait control and is
always accessed without wait states. The peripheral I/O area of this block is not subject
to programmable wait control, either. The only wait control is dependent upon the
execution of each peripheral function.
15
DW71
DWC
Address
FFFFF060H
After reset
FFFFH
14
DW70
13
DW61
12
DW60
11
DW51
10
DW50
9
DW41
8
DW40
7
DW31
6
DW30
5
DW21
4
DW20
3
DW11
2
DW10
1
DW01
0
DW00
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