NEC V854 UPD703006, User Manual

Page: 234 / 417

234
User’s Manual U11969EJ3V0UM00
CHAPTER 8 SERIAL INTERFACE FUNCTION
8.4.3 Configuration
The I
2
C bus is configured with the following hardware.
Table 8-2. I
2
C Bus Configuration
Item Configuration
Register IIC shift register (IIC)
Slave address register (SVA)
Control register IIC clock selection register (IICCL)
IIC status register (IICS)
IIC control register (IICC)
(1) IIC shift register (IIC)
IIC is a register that converts 8-bit serial data into parallel data, and vice versa. IIC is used both for transmission
and reception.
The actual transmission and reception of data is performed by writing data to and reading data from the IIC
shift register.
This register is set by 8-bit memory manipulation instruction. It becomes 00H by RESET input.
(2) Slave address register (SVA)
SVA is a register that sets the local address with 8-bit memory manipulation instruction when used as a slave.
It becomes 00H by RESET input.
(3) SO latch
Retains SDA pin output level.
(4) Wake-up control circuit
Generates interrupt requests when the address value set in the slave address register (SVA) and the reception
address coincide or when an extension code is received.
(5) Clock selector
Selects the sampling clock to be used.
(6) Serial clock counter
Counts the serial clocks to be output or input in transmission/reception and checks whether 8-bit data has
been transmitted/received.
(7) Interrupt request signal generation circuit
Controls generation of interrupt request signals.
I 2 C interrupt is generated by the following two triggers.
• The eighth or the ninth count of the serial clock (set by WTIM bit Note ).
• The generation of an interrupt by the stop condition detection (set by SPIE bit Note ).
Note WTIM bit : bit 3 of IIC control register (IICC)
SPIE bit : bit 4 of IIC control register (IICC)