NEC V854 UPD703006, User Manual

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88
User’s Manual U11969EJ3V0UM00
CHAPTER 4 BUS CONTROL FUNCTION
4.6 Idle State Insertion Function
To facilitate interfacing with low-speed memory devices and meeting the data output float delay time (t
DF
) on
memory read accesses, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The bus cycle
following continuous bus cycles starts after one idle state.
Specifying insertion of the idle state is programmable by using the bus cycle control register (BCC).
Immediately after the system has been reset, idle state insertion is automatically programmed for all memory blocks.
(1) Bus cycle control register (BCC)
This register can be read/written in 16-bit units.
Bit Position Bit Name Function
15, 13, 11, BCn1 Bus Cycle
9, 7, 5, 3, 1 (n = 0 to 7) Specifies insertion of idle state.
0: Not inserted
1: Inserted
n Blocks into Which Idle State Is Inserted
0 Blocks 0/1
1 Blocks 2/3
2 Blocks 4/5
3 Blocks 6/7
4 Blocks 8/9
5 Blocks 10/11
6 Blocks 12/13
7 Blocks 14/15
Cautions 1. Block 0 is reserved for the internal ROM area in the single-chip mode; therefore, no
insertion of the idle state can be specified for block 0 regardless of the BCC settings.
2. The internal RAM area and peripheral I/O area of block 15 are not subject to insertion of
the idle state.
3. Be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to 0. If these bits are set to 1, the operation
is not guaranteed.
15
BC71 BCC
Address
FFFFF062H
After reset
AAAAH
14
0
13
BC61
12
0
11
BC51
10
0
9
BC41
8
0
7
BC31
6
0
5
BC21
4
0
3
BC11
2
0
1
BC01
0
0