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User’s Manual U11969EJ3V0UM00
CHAPTER 3 CPU FUNCTIONS
3.2.2 System register set
System registers control the status of the CPU and hold interrupt information.
Table 3-2. System Register Numbers
To read/write these system registers, specify a system register number indicated by the system register load/store
instruction (LDSR or STSR instruction).
Figure 3-2. Interrupt Source Register (ECR)
Bit Position
Bit Name
Function
31 to 16
FECC
Fatal Error Cause Code
Exception code of NMI. (For exception code, refer to Table 5-1.)
15 to 0
EICC
Exception/Interrupt Cause Code
Exception code of exception/interrupt.
System Register Name
Usage
Operation
These registers save the PC and PSW when an exception
or interrupt occurs. Because only one set of these
registers is available, their contents must be saved when
multiple interrupts are enabled.
These registers save PC and PSW when NMI occurs.
If exception, maskable interrupt, or NMI occurs, this
register will contain information referencing the interrupt
source. The high-order 16 bits of this register are called
FECC, to which exception code of NMI is set. The low-
order 16 bits are called EICC, to which exception code
of exception/interrupt is set (refer to Figure 3-2).
Program status word is collection flags that indicate
program status (instruction execution result) and CPU
status (refer to Figure 3-3).
EIPC
EIPSW
FEPC
FEPSW
ECR
PSW
Status saving registers during
interrupt
Status saving registers for NMI
Interrupt source register
Reserved
Program status word
No.
0
1
2
3
4
5
6 to 31
31
FECC
16 15
EICC
0
0
ECR
After reset
00000000H
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