Intermec EasyCoder 301 – Service Manual Ed. 3
58
Chapter 11 CPU Board
11.8 Schematics,
cont'd.
CPU Board 1-301700-04; Memory Card
A(25:0)
D(15:0)
_PC_OE
_PC_WE
_PC_IORD
_PC_IOWR
_PC_CE1_A
_PC_CE2_A
_CE1
_CE2
A0
A25
D0
D15
R99
10K
_OE
_WE
RESERVED (_IORD)
RESERVED (_IOWR)
_REG
RESET
READY (_IREQ)
_WAIT
_CD1
_CD2
BVD1 (_STSCHG)
BVD2 (_SPKR)
WP (_IOIS16)
RESERVED (_INPACK)
_VS1
_VS2
VCC
VCC
VCC
VPP1
VPP2
GND
GND
GND
GND
A7
A42
A29
A28
A27
A26
A25
A24
A23
A22
A12
A11
A8
A10
A21
A13
A14
A20
A19
A46
A47
A48
A49
A50
A53
A54
A55
A30
A31
A32
A2
A3
A4
A5
A6
A64
A65
A66
A37
A38
A39
A40
A41
A9
A15
A44
A45
A61
A58
A36
A67
A63
A62
A33
A60
A43
A57
A17
A51
A18
A52
A1
A34
A35
A68
A16
A59
_PC_REG_A
PC_RST_A
PC_READY_A
_PC_WAIT_A
_PC_CD1_A
_PC_CD2_A
PC_BVD1_A
PC_WP_A
25
1
2
3
4
5
6
7
8
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A56
Note:
Byte order swapped
VCC
R57
10K
R100
10K
R15
10K
R61
10K
R60
10K
_PC_CE1_B
_PC_CE2_B
_CE1
_CE2
A0
A25
D0
D15
R98
10K
_OE
_WE
RESERVED (_IORD)
RESERVED (_IOWR)
_REG
RESET
READY (_IREQ)
_WAIT
_CD1
_CD2
BVD1 (_STSCHG)
BVD2 (_SPKR)
WP (_IOIS16)
RESERVED (_INPACK)
_VS1
_VS2
VCC
VCC
VCC
VPP1
VPP2
GND
GND
GND
GND
B7
B42
B29
B28
B27
B26
B25
B24
B23
B22
B12
B11
B8
B10
B21
B13
B14
B20
B19
B46
B47
B48
B49
B50
B53
B54
B55
B30
B31
B32
B2
B3
B4
B5
B6
B64
B65
B66
B37
B38
B39
B40
B41
B9
B15
B44
B45
B61
B58
B36
B67
B63
B62
B33
B60
B43
B57
B17
B51
B18
B52
B1
B34
B35
B68
B16
B59
_PC_REG_B
PC_RST_B
PC_READY_B
_PC_WAIT_B
_PC_CD1_B
_PC_CD2_B
PC_BVD1_B
PC_WP_B
25
1
2
3
4
5
6
7
8
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
B56
Note:
Byte order swapped
VCC
R56
10K
R97
10K
R14
10K
R59
10K
R58
10K