UPI-41A/41AH/42/42AH USER’S MANUAL
An interrupt or Call to a subroutine causes the contents
of the program counter to be stored in one of the 8
register pairs of the program counter stack.
DATA
STACK
MEMORY
POINTER
LOCATION
111
23
22
110
21
20
101
19
18
100
17
16
011
15
14
010
13
12
001
11
10
000
PSW
(4 – 7)
PC
(8 – 9)
9
PC
(4 – 7)
PC
(0 – 3)
8
MSB
LSB
Figure 2-7. Program Counter Stack
A 3-bit Stack Pointer which is part of the Program
Status Word (PSW) determines the stack pair to be
used at a given time. The stack pointer is initialized by
a RESET signal to 00H which corresponds to RAM
locations 8 and 9.
The first call or interrupt results in the program coun-
ter and PSW contents being transferred to RAM loca-
tions 8 and 9 in the format shown in Figure 2-7. The
stack pointer is automatically incremented by 1 to point
to location is 10 and 11 in anticipation of another
CALL.
Nesting of subroutines within subroutines can continue
up to 8 levels without overflowing the stack. If overflow
does occur the deepest address stored (locations 8 and
9) will be overwritten and lost since the stack pointer
overflows from 07H to 00H. Likewise, the stack pointer
will underflow from 00H to 07H.
The end of a subroutine is signaled by a return instruc-
tion, either RET or RETR. Each instruction will auto-
matically decrement the Stack Pointer and transfer the
contents of the proper RAM register pair to the Pro-
gram Counter.
PROGRAM STATUS WORD
The 8-bit program status word illustrated in Figure 2-8
is used to store general information about program exe-
cution. In addition to the 3-bit Stack Pointer discussed
previously, the PSW includes the following flags:
#
CY Ð Carry
#
AC Ð Auxiliary Carry
#
F
0
Ð Flag 0
#
BS Ð Register Bank Select
231318 – 12
Figure 2-8. Program Status Word
The Program Status Word (PSW) is actually a collec-
tion of flip-flops located throughout the machine which
are read or written as a whole. The PSW can be loaded
to or from the accumulator by the MOV A, PSW or
MOV PSW, A instructions. The ability to write directly
to the PSW allows easy restoration of machine status
after a power-down sequence.
The upper 4 bits of the PSW (bits 4, 5, 6, and 7) are
stored in the PC Stack with every subroutine CALL or
interrupt vector. Restoring the bits on a return is op-
tional. The bits are restored if an RETR instruction is
executed, but not if an RET is executed.
PSW bit definitions are as follows:
#
Bits 0 – 2 Stack Pointer Bits S
0
, S
1
, S
2
#
Bit 3 Not Used
#
Bit 4 Working Register Bank
0
e
Bank 0
1
e
Bank 1
#
Bit 5 Flag 0 bit (F
0
)
This is a general purpose flag which can be cleared
or complemented and tested with conditional jump
instructions. It may be used during data transfer to
an external processor.
#
Bit 6 Auxiliary Carry (AC)
The flag status is determined by an ADD instruc-
tion and is used by the Decimal Adjustment instruc-
tion DAA
#
Bit 7 Carry (CY)
The flag indicates that a previous operation resulted
in overflow of the accumulator.
CONDITIONAL BRANCH LOGIC
Conditional Branch Logic in the UPI-41AH, 42AH al-
lows the status of various processor flags, inputs, and
other hardware functions to directly affect program ex-
ecution. The status is sampled in state 3 of the first
cycle.
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