UPI-41A/41AH/42/42AH USER’S MANUAL
EXTERNAL ACCESS
The UPI family has an External Access mode (EA)
which puts the processor into a test mode. This mode
allows the user to disable the internal program memory
and execute from external memory. External Access
mode is useful in testing because it allows the user to
test the processor’s functions directly. It is only useful
for testing since this mode uses D
0
– D
7
, PORTS 10 – 17
and PORTS 20 – 22.
This mode is invoked by connecting the EA pin to 5V.
The 11-bit current program counter contents then come
out on PORTS 10 – 17 and PORTS 20 – 22 after the
SYNC output goes high. (PORT 10 is the least signifi-
cant bit.) The desired instruction opcode is placed on
D
0
– D
7
before the start of state S
1
. During state S
1
, the
opcode is sampled from D
0
– D
7
and subsequently exe-
cuted in place of the internal program memory con-
tents.
The program counter contents are multiplexed with the
I/O port data on PORTS 10 – 17 and PORTS 20 – 22.
The I/O port data may be demultiplexed using an ex-
ternal latch on the rising edge of SYNC. The program
counter contents may be demultiplexed similarly using
the trailing edge of SYNC.
Reading and/or writing the Data Bus Buffer registers is
still allowed although only when D
0
– D
7
are not being
sampled for opcode data. In practice, since this sam-
pling time is not known externally, reads or writes on
the system bus are done during SYNC high time. Ap-
proximately 600 ns are available for each read or write
cycle.
POWER DOWN MODE
(UPI-41AH/42AH ONLY)
Extra circuitry is included in the UPI-41AH/42AH
version to allow low-power, standby operation. Power
is removed from all system elements except the inter-
nal data RAM in the low-power mode. Thus the con-
tents of RAM can be maintained and the device draws
only 10 to 15% of its normal power.
The V
CC
pin serves as the 5V power supply pin for all
of the UPI-41AH/42AH version’s circuitry except the
data RAM array. The V
DD
pin supplies only the RAM
array. In normal operation, both V
CC
and V
DD
are
connected to the same 5V power supply.
To enter the Power-Down mode, the RESET signal to
the UPI is asserted. This ensures the memory will not
be inadvertently altered by the UPI during power-
down. The V
CC
pin is then grounded while V
DD
is
maintained at 5V. Figure 4-4 illustrates a recommended
Power-Down sequence. The sequence typically occurs
as follows:
1) Imminent power supply failure is detected by user
defined circuitry. The signal must occur early
enough to guarantee the UPI-41AH/42AH can save
all necessary data before V
CC
falls outside normal
operating tolerance.
2) A ‘‘Power Failure’’ signal is used to interrupt the
processor (via a timer overflow interrupt, for in-
stance) and call a Power Failure service routine.
3) The Power Failure routine saves all important data
and machine status in the RAM array. The routine
may also initiate transfer of a backup supply to the
V
DD
pin and indicate to external circuitry that the
Power Failure routine is complete.
4) A RESET signal is applied by external hardware to
guarantee data will not be altered as the power sup-
ply falls out of limits. RESET must be low until V
CC
reaches ground potential.
Recovery from the Power-Down mode can occur as
any other power-on sequence. An external 1
m
fd capac-
itor on the RESET input will provide the necessary
initialization pulse.
231318 – 31
Figure 4-4. Power-Down Sequence
55
