UPI-41A/41AH/42/42AH USER’S MANUAL
231318 – 35
Figure 5-4. Writing Data to DBBIN
Write Data to DBBIN
The sequence for writing data to the DBBIN register is
shown in Figure 5-4. This operation causes the system
Data Bus contents to be transferred to the DBBIN reg-
ister and the IBF flag is set. Also, the F
1
flag is cleared
(F
1
e
0) and an interrupt request is generated. When
the IBF interrupt is enabled, a jump to location 3 will
occur. The interrupt request is cleared upon entering
the IBF service routine or by a system RESET input.
Writing Commands to DBBIN
The sequence for writing commands to the DBBIN reg-
ister is shown in Figure 5-5. This sequence is identical
to a data write except that the A
0
input is latched in the
F
1
flag (F
1
e
1). The IBF flag is set and an interrupt
request is generated when the master writes a command
to DBB.
Operations of Data Bus Registers
The UPI-41A/41AH/42/42AH Microcomputer con-
trols the transfer of DBB data to its accumulator by
executing INput and OUTput instructions. An IN
A,DBB instruction causes the contents to be trans-
ferred to the UPI accumulator and the IBF flag is
cleared.
The OUT DBB,A instruction causes the contents of the
accumulator to be transferred to the DBBOUT register.
The OBF flag is set.
The UPI’s data bus buffer interface is applicable to a
variety of microprocessors including the 8086, 8088,
8085AH, 8080, and 8048.
A description of the interface to each of these proces-
sors follows.
231318 – 36
Figure 5-5. Writing Commands to DBBIN
DESIGN EXAMPLES
8085AH Interface
Figure 5-6 illustrates an 8085AH system using a UPI-
41A/41AH/42/42AH. The 8085AH system uses a
multiplexed address and data bus. During I/O the 8
upper address lines (A
8
– A
15
) contain the same I/O
address as the lower 8 address/data lines (A
0
– A
7
);
therefore I/O address decoding is done using only the
upper 8 lines to eliminate latching of the address. An
8205 decoder provides address decoding for both the
UPI and the 8237. Data is transferred using the two
DMA handshaking lines of PORT 2. The 8237 per-
forms the actual bus transfer operation. Using the UPI-
41A/41AH/42/42AH’s OBF master interrupt, the
UPI notifies the 8085AH upon transfer completion us-
ing the RST 5.5 interrupt input. The IBF master inter-
rupt is not used in this example.
8088 Interface
Figure 5-7 illustrates a UPI-41A/41AH/42/42AH in-
terface to an 8088 minimum mode system. Two 8-bit
latches are used to demultiplex the address and data
bus. The address bus is 20-lines wide. For I/O only, the
lower 16 address lines are used, providing an address-
ing range of 64K. UPI address selection is accom-
plished using an 8205 decoder. The A
0
address line of
the bus is connected to the corresponding UPI input for
register selection. Since the UPI is polled by the 8088,
neither DMA nor master interrupt capabilities of the
UPI are used in the figure.
8086 Interface
The UPI-41A/41AH/42/42AH can be used on an
8086 maximum mode system as shown in Figure 5-8.
The address and data bus is demultiplexed using three
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