UPI-41A/41AH/42/42AH USER’S MANUAL
Cycle Counter
The output of the state counter is divided by 5 in the
cycle counter to generate a signal which defines a ma-
chine cycle. This signal is call SYNC and is available
continuously on the SYNC output pin. It can be used
to synchronize external circuitry or as a general pur-
pose clock output. It is also used for synchronizing sin-
gle-step.
Frequency Reference
The external crystal provides high speed and accurate
timing generation. A crystal frequency of 5.9904 MHz
is useful for generation of standard communication fre-
quencies by the UPI-41A/41AH/42/42AH. However,
if an accurate frequency reference and maximum proc-
essor speed are not required, an inductor and capacitor
may be used in place of the crystal as shown in Figure
2-11.
A recommended range of inductance and capacitance
combinations is given below:
#
L
e
130
m
H corresponds to 3 MHz
#
L
e
45
m
H corresponds to 5 MHz
An external clock signal can also be used as a frequency
reference to the UPI-41A/41AH/42/42AH; however,
the levels are
not
TTL compatible. The signal must be
in the 1 – 12.5 MHz frequency range depending on
which UPI is used. Refer to Table 1-2. The signal must
be connected to pins XTAL 1 and XTAL 2 by buffers
with a suitable pull-up resistor to guarantee that a logic
‘‘1’’ is above 3.8 volts. The recommended connection is
shown in Figure 2-12.
231318 – 16
Figure 2-12. Recommended Connection
For External Clock Signal
INTERVAL TIMER/EVENT COUNTER
The UPI-41A/41AH/42/42AH has a resident 8-bit
timer/counter which has several software selectable
modes of operation. As an interval timer, it can gener-
ate accurate delays from 80 microseconds to 20.48 mil-
liseconds without placing undue burden on the proces-
sor. In the counter mode, external events such as switch
closures or tachometer pulses can be counted and used
to direct program flow.
Timer Configuration
Figure 2-13 illustrates the basic timer/counter configu-
ration. An 8-bit register is used to count pulses from
either the internal clock and prescaler or from an exter-
nal source. The counter is presettable and readable with
two MOV instructions which transfer the contents of
the accumulator to the counter and vice-versa (i.e.
MOV T, A and MOV A, T). The counter is stopped by
a RESET or STOP TCNT instruction and remains
stopped until restarted either as a timer (START T in-
struction) or as a counter (START CNT instruction).
Once started, the counter will increment to its maxi-
mum count (FFH) and overflow to zero continuing its
count until stopped by a STOP TCNT instruction or
RESET.
The increment from maximum count to zero (overflow)
results in setting the Timer Flag (TF) and generating an
interrupt request. The state of the overflow flag is test-
able with the conditional jump instruction, JTF. The
flag is reset by executing a JTF or by a RESET signal.
The timer interrupt request is stored in a latch and
ORed with the input buffer full interrupt request. The
timer interrupt can be enabled or disabled independent
of the IBF interrupt by the EN TCNTI and DIS
TCTNI instructions. If enabled, the counter overflow
will cause a subroutine call to location 7 where the tim-
er service routine is stored. If the timer and Input Buff-
er Full interrupts occur simultaneously, the IBF source
will be recognized and the call will be to location 3.
Since the timer interrupt is latched, it will remain pend-
ing until the DBBIN register has been serviced and will
immediately be recognized upon return from the serv-
ice routine. A pending timer interrupt is reset by the
initiation of a timer interrupt service routine.
Event Counter Mode
The STRT CNT instruction connects the TEST 1 input
pin to the counter input and enables the counter. Note
this instruction does not clear the counter. The counter
is incremented on high to low transitions of the TEST 1
input. The TEST 1 input must remain high for a mini-
mum of one state in order to be registered (250 ns at
12 MHz). The maximum count frequency is one count
per three instruction cycles (267 kHz at 12 MHz).
There is no minimum frequency limit.
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