UPI-41A/41AH/42/42AH USER’S MANUAL
accessed intermediate results. Other locations in data
memory are addressed indirectly by using R
0
or R
1
to
specify the desired address.
231318 – 11
Figure 2-6. Data Memory Map
Working Registers
Dual banks of eight working registers are included in
the UPI-41A/41AH/42/42AH data memory. Loca-
tions 0 – 7 make up register bank 0 and locations 24 – 13
form register bank 1. A RESET signal automatically
selects register bank 0. When bank 0 is selected, refer-
ences to R
0
– R
7
in UPI-41A/41AH/42/42AH instruc-
tions operate on locations 0 – 7 in data memory. A ‘‘se-
lect register bank’’ instruction is used to selected be-
tween the banks during program execution. If the in-
struction SEL RB1 (Select Register Bank 1) is execut-
ed, then program references to R
0
– R
7
will operate on
locations 24 – 31. As stated previously, registers 0 and 1
in the active register bank are used as indirect address
registers for all locations in data memory.
Register bank 1 is normally reserved for handling inter-
rupt service routines, thereby preserving the contents of
the main program registers. The SEL RB1 instruction
can be issued at the beginning of an interrupt service
routine. Then, upon return to the main program, an
RETR (return & restore status) instruction will auto-
matically restore the previously selected bank. During
interrupt processing, registers in bank 0 can be accessed
indirectly using R
0
Ê
and R
1
Ê
.
If register bank 1 is not used, registers 24 – 31 can still
serve as additional scratch pad memory.
Program Counter Stack
RAM locations 8 – 23 are used as an 8-level program
counter stack. When program control is temporarily
passed from the main program to a subroutine or inter-
rupt service routine, the 10-bit program counter and
bits 4 – 7 of the program status word (PSW) are stored
in two stack locations. When control is returned to the
main program via an RETR instruction, the program
counter and PSW bits 4 – 7 are restored. Returning via
an RET instruction does not restore the PSW bits,
however. The program counter stack is addressed by
three stack pointer bits in the PSW (bits 0 – 2). Opera-
tion of the program counter stack and the program
status word is explained in detail in the following sec-
tions.
The stack allows up to eight levels of subroutine ‘nest-
ing’; that is, a subroutine may call a second subroutine,
which may call a third, etc., up to eight levels. Unused
stack locations can be used as scratch pad memory.
Each unused level of subroutine nesting provides two
additional RAM locations for general use.
The following sections provide a detailed description of
the Program Counter Stack and the Program Status
Word.
PROGRAM COUNTER
The UPI-41A/41AH/42/42AH microcomputer has a
10-bit program counter (PC) which can directly ad-
dress any of the 1024, 2048, or 4096 locations in pro-
gram memory. The program counter always contains
the address of the next instruction to be executed and is
normally incremented sequentially for each instruction
to be executed when each instruction fetches occurs.
When control is temporarily passed from the main pro-
gram to a subroutine or an interrupt routine, however,
the PC contents must be altered to point to the address
of the desired routine. The stack is used to save the
current PC contents so that, at the end of the routine,
main program execution can continue. The program
counter is initialized to zero by a RESET signal.
PROGRAM COUNTER STACK
The Program Counter Stack is composed of 16 loca-
tions in Data Memory as illustrated in Figure 2-7.
These RAM locations (8 through 23) are used to store
the 10-bit program counter and 4 bits of the program
status word.
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